GitHub/qpcpp
1
0
Fork 0
mirror of https://github.com/QuantumLeaps/qpcpp.git synced 2025-01-28 06:02:56 +08:00
Code Issues Projects Releases Wiki Activity

5.9.5

Browse Source
This commit is contained in:
Quantum Leaps 2017-07-20 13:06:27 -04:00
parent 8c2917abc9
commit 1b45201043
82 changed files with 3552 additions and 4357 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
3rd_party/efm32pg1b/gnu/startup_efm32pg1b.c vendored
View File

@ -1,8 +1,8 @@
/* File: startup_efm32pg1b.c
* Purpose: startup file for EFM32PG1B devices.
* Should be used with GCC 'GNU Tools ARM Embedded'
* Version: CMSIS 4.3.0
* Date: 02 May 2016
* Version: CMSIS 5.0.1
* Date: 18 July 2017
*
* Created from the CMSIS template for the specified device
* Quantum Leaps, www.state-machine.com
@ -214,6 +214,7 @@ void NMI_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_nmi: .asciz \"NMI\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/
@ -224,6 +225,7 @@ void MemManage_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_mem: .asciz \"MemManage\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/
@ -234,6 +236,7 @@ void HardFault_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_hrd: .asciz \"HardFault\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/
@ -244,6 +247,7 @@ void BusFault_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_bus: .asciz \"BusFault\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/
@ -254,6 +258,7 @@ void UsageFault_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_usage: .asciz \"UsageFault\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/
@ -264,6 +269,7 @@ void Default_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_dflt: .asciz \"Default\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/

13
3rd_party/efm32pg1b/iar/startup_efm32pg1b.s vendored
View File

@ -2,7 +2,7 @@
; * @file startup_efm32pg1b.s for IAR ARM assembler
; * @brief CMSIS Cortex-M4F Core Device Startup File for TM4C123GH6PM
; * @version CMSIS 4.3.0
; * @date 07 May 2016
; * @date 07 Sep 2016
; *
; * @description
; * Created from the CMSIS template for the specified device
@ -130,6 +130,17 @@ __Vectors_Size EQU __Vectors_End - __Vectors
EXTERN __iar_program_start
Reset_Handler
BL SystemInit ; CMSIS system initialization
; pre-fill the CSTACK with 0xDEADBEEF...................
LDR r0,=0xDEADBEEF
MOV r1,r0
LDR r2,=sfb(CSTACK)
LDR r3,=sfe(CSTACK)
Reset_stackInit_fill:
STMIA r2!,{r0,r1}
CMP r2,r3
BLT.N Reset_stackInit_fill
BL __iar_program_start ; IAR startup code
;.............................................................................
PUBWEAK NMI_Handler

10
3rd_party/ek-lm3s6965/gnu/startup_LM3S6965.c vendored
View File

@ -1,8 +1,8 @@
/* File: startup_LM3S6965.c for GCC-ARM
* Purpose: startup file for LM3S6965 Cortex-M3 device.
* Should be used with GCC 'GNU Tools ARM Embedded'
* Version: CMSIS 4.3.0
* Date: 06 August 2015
* Version: CMSIS 5.0.1
* Date: 18 July 2017
*
* Created from the CMSIS template for the specified device
* Quantum Leaps, www.state-machine.com
@ -247,6 +247,7 @@ void NMI_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_nmi: .asciz \"NMI\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/
@ -257,6 +258,7 @@ void MemManage_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_mem: .asciz \"MemManage\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/
@ -267,6 +269,7 @@ void HardFault_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_hrd: .asciz \"HardFault\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/
@ -277,6 +280,7 @@ void BusFault_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_bus: .asciz \"BusFault\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/
@ -287,6 +291,7 @@ void UsageFault_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_usage: .asciz \"UsageFault\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/
@ -297,6 +302,7 @@ void Default_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_dflt: .asciz \"Default\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/

10
3rd_party/ek-tm4c123gxl/gnu/startup_TM4C123GH6PM.c vendored
View File

@ -1,8 +1,8 @@
/* File: startup_TM4C123GH6PM.c
* Purpose: startup file for TM4C123GH6PM Cortex-M4 device.
* Should be used with GCC 'GNU Tools ARM Embedded'
* Version: CMSIS 4.3.0
* Date: 20 August 2015
* Version: CMSIS 5.0.1
* Date: 18 July 2017
*
* Created from the CMSIS template for the specified device
* Quantum Leaps, www.state-machine.com
@ -404,6 +404,7 @@ void NMI_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_nmi: .asciz \"NMI\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/
@ -414,6 +415,7 @@ void MemManage_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_mem: .asciz \"MemManage\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/
@ -424,6 +426,7 @@ void HardFault_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_hrd: .asciz \"HardFault\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/
@ -434,6 +437,7 @@ void BusFault_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_bus: .asciz \"BusFault\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/
@ -444,6 +448,7 @@ void UsageFault_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_usage: .asciz \"UsageFault\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/
@ -454,6 +459,7 @@ void Default_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_dflt: .asciz \"Default\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/

2
3rd_party/launchxl2-tms57012/ti/launchxl2-tms57012_ti.dil vendored
View File

@ -1,4 +1,4 @@
# TMS570LS1224PGE 09/01/16 09:23:23
# TMS570LS1224PGE 08/29/16 16:25:37
#
ARCH=TMS570LS1224PGE
#

10
3rd_party/mbed-lpc1768/gnu/startup_LPC17xx.c vendored
View File

@ -1,8 +1,8 @@
/* File: startup_LPC17xx.c
* Purpose: startup file for LPC17xx Cortex-M3 devices.
* Should be used with GCC 'GNU Tools ARM Embedded'
* Version: CMSIS 4.3.0
* Date: 06 August 2015
* Version: CMSIS 5.0.1
* Date: 18 July 2017
*
* Created from the CMSIS template for the specified device
* Quantum Leaps, www.state-machine.com
@ -227,6 +227,7 @@ void NMI_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_nmi: .asciz \"NMI\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/
@ -237,6 +238,7 @@ void MemManage_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_mem: .asciz \"MemManage\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/
@ -247,6 +249,7 @@ void HardFault_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_hrd: .asciz \"HardFault\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/
@ -257,6 +260,7 @@ void BusFault_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_bus: .asciz \"BusFault\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/
@ -267,6 +271,7 @@ void UsageFault_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_usage: .asciz \"UsageFault\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/
@ -277,6 +282,7 @@ void Default_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_dflt: .asciz \"Default\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/

10
3rd_party/nucleo-l053r8/gnu/startup_stm32l053xx.c vendored
View File

@ -1,8 +1,8 @@
/* File: startup_stm32l053xx.c for GNU-ARM
* Purpose: startup file for LM3S6965 Cortex-M3 device.
* Should be used with GCC 'GNU Tools ARM Embedded'
* Version: CMSIS 4.3.0
* Date: 20 August 2015
* Version: CMSIS 5.0.1
* Date: 18 July 2017
*
* Created from the CMSIS template for the specified device
* Quantum Leaps, www.state-machine.com
@ -217,6 +217,7 @@ void NMI_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_nmi: .asciz \"NMI\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/
@ -227,6 +228,7 @@ void MemManage_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_mem: .asciz \"MemManage\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/
@ -237,6 +239,7 @@ void HardFault_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_hrd: .asciz \"HardFault\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/
@ -247,6 +250,7 @@ void BusFault_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_bus: .asciz \"BusFault\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/
@ -257,6 +261,7 @@ void UsageFault_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_usage: .asciz \"UsageFault\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/
@ -267,6 +272,7 @@ void Default_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_dflt: .asciz \"Default\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/

10
3rd_party/nucleo-l152re/gnu/startup_stm32l1xx.c vendored
View File

@ -1,8 +1,8 @@
/* File: startup_stm32l1xx.c for GNU-ARM
* Purpose: startup file for STM32L1xx Cortex-M3 device.
* Should be used with GCC 'GNU Tools ARM Embedded'
* Version: CMSIS 4.3.0
* Date: 2 March 2016
* Version: CMSIS 5.0.1
* Date: 18 July 2017
*
* Created from the CMSIS template for the specified device
* Quantum Leaps, www.state-machine.com
@ -272,6 +272,7 @@ void NMI_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_nmi: .asciz \"NMI\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/
@ -282,6 +283,7 @@ void MemManage_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_mem: .asciz \"MemManage\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/
@ -292,6 +294,7 @@ void HardFault_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_hrd: .asciz \"HardFault\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/
@ -302,6 +305,7 @@ void BusFault_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_bus: .asciz \"BusFault\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/
@ -312,6 +316,7 @@ void UsageFault_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_usage: .asciz \"UsageFault\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/
@ -322,6 +327,7 @@ void Default_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_dflt: .asciz \"Default\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/

10
3rd_party/stm32f4-discovery/gnu/startup_stm32f4xx.c vendored
View File

@ -1,8 +1,8 @@
/* File: startup_stm32f4xx.c
* Purpose: startup file for stm32f4xx Cortex-M4 device.
* Should be used with GCC 'GNU Tools ARM Embedded'
* Version: CMSIS 4.3.0
* Date: 20 August 2015
* Version: CMSIS 5.0.1
* Date: 18 July 2017
*
* Created from the CMSIS template for the specified device
* Quantum Leaps, www.state-machine.com
@ -313,6 +313,7 @@ void NMI_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_nmi: .asciz \"NMI\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/
@ -323,6 +324,7 @@ void MemManage_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_mem: .asciz \"MemManage\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/
@ -333,6 +335,7 @@ void HardFault_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_hrd: .asciz \"HardFault\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/
@ -343,6 +346,7 @@ void BusFault_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_bus: .asciz \"BusFault\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/
@ -353,6 +357,7 @@ void UsageFault_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_usage: .asciz \"UsageFault\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/
@ -363,6 +368,7 @@ void Default_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_dflt: .asciz \"Default\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/

0
3rd_party/stm32f7-discovery/arm/startup_stm32f4xx.s → 3rd_party/stm32f7-discovery/arm/startup_stm32f746xx.s vendored
View File

6
3rd_party/stm32f7-discovery/gnu/startup_stm32f4xx.c → 3rd_party/stm32f7-discovery/gnu/startup_stm32f746xx.c vendored
View File

@ -344,6 +344,7 @@ void NMI_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_nmi: .asciz \"NMI\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/
@ -354,6 +355,7 @@ void MemManage_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_mem: .asciz \"MemManage\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/
@ -364,6 +366,7 @@ void HardFault_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_hrd: .asciz \"HardFault\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/
@ -374,6 +377,7 @@ void BusFault_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_bus: .asciz \"BusFault\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/
@ -384,6 +388,7 @@ void UsageFault_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_usage: .asciz \"UsageFault\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/
@ -394,6 +399,7 @@ void Default_Handler(void) {
" mov r1,#1\n\t"
" b assert_failed\n\t"
"str_dflt: .asciz \"Default\"\n\t"
" .align 2\n\t"
);
}
/*..........................................................................*/

132
README.md
View File

@ -4,92 +4,92 @@
View QP/C++ Revision History at:
https://state-machine.com/qpcpp/history.html
---------------------------------------------------------------------------
---------------------------------------------------------------------------
# About QP/C++
QP/C++ (Quantum Platform in C++) is a lightweight, open source software
framework/RTOS for building reactvie real-time embedded applications
framework/RTOS for building reactvie real-time embedded applications
as systems of cooperating, event-driven active objects (actors). The
QP/C++ framework is a member of a larger [QP] family consisting of
QP/C++ framework is a member of a larger [QP] family consisting of
QP/C, QP/C++, and QP-nano frameworks, which are all strictly quality
controlled, thoroughly documented, and commercially licensable.
## Safer Model of Concurrency
The [QP] framework family is based on the [Active Object] (**actor**)
design pattern, which inherently supports and automatically enforces the
following best practices of concurrent programming:
- Keep data isolated and bound to active objects' threads. Threads should
hide (**encapsulate**) their private data and other resources, and not
share them with the rest of the system.
- Communicate among active object threads **asynchronously** via event
objects. Using asynchronous events keeps the threads running truly
independently, **without blocking** on each other.
- Active object threads should spend their lifetime responding to incoming
events, so their mainline should consist of an **event-loop** that handles
events one at a time (to completion), thus avoiding any concurrency hazards
within an active object thread itself.
This architecture is generally **safer**, more responsive and easier to
understand and maintain than the shared-state concurrency of a conventional
RTOS. It also provides higher level of abstraction and the right
abstractions to effectively apply **modeling** and **code generation** to
deeply embedded real-time systems.
## Safer Model of Concurrency
The [QP] framework family is based on the [Active Object] (**actor**)
design pattern, which inherently supports and automatically enforces the
following best practices of concurrent programming:
- Keep data isolated and bound to active objects' threads. Threads should
hide (**encapsulate**) their private data and other resources, and not
share them with the rest of the system.
- Communicate among active object threads **asynchronously** via event
objects. Using asynchronous events keeps the threads running truly
independently, **without blocking** on each other.
- Active object threads should spend their lifetime responding to incoming
events, so their mainline should consist of an **event-loop** that handles
events one at a time (to completion), thus avoiding any concurrency hazards
within an active object thread itself.
This architecture is generally **safer**, more responsive and easier to
understand and maintain than the shared-state concurrency of a conventional
RTOS. It also provides higher level of abstraction and the right
abstractions to effectively apply **modeling** and **code generation** to
deeply embedded real-time systems.
## Hierarchical State Machines
The behavior of active objects is specified in QP/C++ by means of
[Hierarchical State Machines] (UML statecharts). The framework
supports manual coding of UML state machines in C as well as automatic
**code generation** by means of the free [QM] modeling tool.
[Hierarchical State Machines] (UML statecharts). The framework
supports manual coding of UML state machines in C as well as automatic
**code generation** by means of the free [QM] modeling tool.
## Built-in Real-Time Kernels
The QP/C++ framework can run on bare-metal single-chip microcontrollers,
completely replacing a traditional RTOS. The framework contains a selection
of **built-in real-time kernels**, such as the cooperative QV kernel, the
preemptive non-blocking QK kernel, and the preemptive, blocking QXK kernel
that provides all the features you might expect from a traditional RTOS.
Native QP ports and ready-to-use examples are provided for major CPUs, such
as ARM Cortex-M (M0/M0+/M3/M4/M7).
## Traditional RTOS/OS
QP/C++ can also work with a traditional RTOS, such as ThreadX, embOS,
uC/OS-II and TI-RTOS, as well as with (embedded) Linux (POSIX) and Windows.
The QP/C++ framework can run on bare-metal single-chip microcontrollers,
completely replacing a traditional RTOS. The framework contains a selection
of **built-in real-time kernels**, such as the cooperative QV kernel, the
preemptive non-blocking QK kernel, and the preemptive, blocking QXK kernel
that provides all the features you might expect from a traditional RTOS.
Native QP ports and ready-to-use examples are provided for major CPUs, such
as ARM Cortex-M (M0/M0+/M3/M4/M7).
## Traditional RTOS/OS
QP/C++ can also work with a traditional RTOS, such as ThreadX, embOS,
uC/OS-II and TI-RTOS, as well as with (embedded) Linux (POSIX) and Windows.
## Maturity
With 60,000 downloads a year, the [QP] family is the most popular such
solution on the embedded software market. It provides a modern, reusable
architecture for embedded applications, which combines the active-object
With 60,000 downloads a year, the [QP] family is the most popular such
solution on the embedded software market. It provides a modern, reusable
architecture for embedded applications, which combines the active-object
model of concurrency with hierarchical state machines.
---------------------------------------------------------------------------
---------------------------------------------------------------------------
# Getting Started with QP/C++
The following "Getting Started with QP/C++" guide provides step-by-step
instructions on how to download, install, and get started with QP/C++ quickly:
The following "Getting Started with QP/C++" guide provides step-by-step
instructions on how to download, install, and get started with QP/C++ quickly:
https://state-machine.com/doc/AN_Getting_Started_with_QPCpp.pdf
The guide also contains a tutorial, in which you build a simple "Blinky"
application.
> NOTE: QP/C++ can be unzipped anywhere in your file system, but the
recommended location is `C:\qp\qpcpp` on Windows and `~/qp/qpcpp`
The guide also contains a tutorial, in which you build a simple "Blinky"
application.
> NOTE: QP/C++ can be unzipped anywhere in your file system, but the
recommended location is `C:\qp\qpcpp` on Windows and `~/qp/qpcpp`
on Linux/MacOS.
---------------------------------------------------------------------------
---------------------------------------------------------------------------
# QP/C++ Documentation
The **QP/C++ Manual** is located online at:
- https://state-machine.com/qpcpp
---------------------------------------------------------------------------
# How to get help?
- [Free Support Forum](https://sourceforge.net/p/qpc/discussion/668726)
- [Bug Reports](https://sourceforge.net/p/qpc/bugs/)
- [Feature Requests](https://sourceforge.net/p/qpc/feature-requests/)
- [Quantum Leaps website](https://state-machine.com)
- [Quantum Lepas licensing](https://state-machine.com/licensing)
---------------------------------------------------------------------------
# How to get help?
- [Free Support Forum](https://sourceforge.net/p/qpc/discussion/668726)
- [Bug Reports](https://sourceforge.net/p/qpc/bugs/)
- [Feature Requests](https://sourceforge.net/p/qpc/feature-requests/)
- [Quantum Leaps website](https://state-machine.com)
- [Quantum Lepas licensing](https://state-machine.com/licensing)
- [info@state-machine.com](mailto:info@state-machine.com)
[QP]: <https://state-machine.com/products/#QP>
[QM]: <https://state-machine.com/qm>
[Active Object]: <https://state-machine.com/doc/concepts#Active>
[Hierarchical State Machines]: <https://state-machine.com/doc/concepts#HSM>
[QM]: <https://state-machine.com/qm>
[Active Object]: <https://state-machine.com/doc/concepts#Active>
[Hierarchical State Machines]: <https://state-machine.com/doc/concepts#HSM>

2
doxygen/Doxyfile
View File

@ -5,7 +5,7 @@
#---------------------------------------------------------------------------
DOXYFILE_ENCODING = UTF-8
PROJECT_NAME = "QP/C++"
PROJECT_NUMBER = "5.9.4"
PROJECT_NUMBER = "5.9.5"
PROJECT_BRIEF =
PROJECT_LOGO = images/header_logo_ql.png
OUTPUT_DIRECTORY =

2
doxygen/Doxyfile-CHM
View File

@ -5,7 +5,7 @@
#---------------------------------------------------------------------------
DOXYFILE_ENCODING = UTF-8
PROJECT_NAME = "QP/C++"
PROJECT_NUMBER = "5.9.4"
PROJECT_NUMBER = "5.9.5"
PROJECT_BRIEF =
PROJECT_LOGO = images/header_logo_ql.png
OUTPUT_DIRECTORY =

16
doxygen/history.dox
View File

@ -2,6 +2,22 @@ namespace QP {
/** @page history Revision History
@section qpcpp_5_9_5 Version 5.9.5, 2017-07-20
This release fixes the following bug:
- <a href="https://sourceforge.net/p/qpc/bugs/178/" class="extern">bug#178</a> "GNU-ARM compiler reports "Error: unaligned opcodes..." in startup code for QP/C/C++/nano examples". The bug fix entails modifying the startup code for the GNU-ARM compiler in the `3rd_party` directory. Specifically, the proper alignment directives have been added to the inline assembly in the exception handlers.
This release fixes the naming problem of the startup code for the
STM32F7-Discovery board (in the `3rd_party/stm32f7-discovery/gnu/ and arm/`
directories), where the startup code was renamed from `startup_stm32f4xx.c/s`
to `startup_stm32f746xx.c/s`. The change has been also made in the example
projects for the STM32F7-Discovery board (for ARM-KEIL and GNU-ARM toolsets).
Finally, this release modifies the example code (mostly `bsp.cpp` files)
so that the Q_DEFINE_THIS_FILE() macro is used consistently *outside*
a namespace at the top of the file scope.
-----------------------------------------------------------------------------
@section qpcpp_5_9_4 Version 5.9.4, 2017-07-07
This release adds Thread-Local Storage (TLS) feature for the dual-mode
QXK kernel (see @ref qxk_tls).

6
doxygen/make.bat
View File

@ -1,8 +1,8 @@
@echo off
:: ==========================================================================
:: Product: QP/C++ script for generating Doxygen documentation
:: Last Updated for Version: 5.9.4
:: Date of the Last Update: 2017-07-05
:: Last Updated for Version: 5.9.5
:: Date of the Last Update: 2017-07-19
::
:: Q u a n t u m L e a P s
:: ---------------------------
@ -38,7 +38,7 @@ echo usage:
echo make
echo make -CHM
set VERSION=5.9.4
set VERSION=5.9.5
:: Generate Resource Standard Metrics for QP/C++ .............................
set DOXHOME="C:\tools\doxygen\bin"

6312
doxygen/metrics.dox
View File

File diff suppressed because it is too large Load Diff

8
examples/arm-cm/dpp_efm32-slstk3401a/qk/bsp.cpp
View File

@ -1,7 +1,7 @@
///***************************************************************************
// Product: DPP example, EFM32-SLSTK3401A board, preemptive QK kernel
// Last Updated for Version: 5.9.0
// Date of the Last Update: 2017-05-09
// Last Updated for Version: 5.9.5
// Date of the Last Update: 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -41,11 +41,11 @@
#include "em_usart.h" // USART (SiLabs)
// add other drivers if necessary...
Q_DEFINE_THIS_FILE
// namespace DPP *************************************************************
namespace DPP {
Q_DEFINE_THIS_FILE
// !!!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
// Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
// DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!

8
examples/arm-cm/dpp_efm32-slstk3401a/qv/bsp.cpp
View File

@ -1,7 +1,7 @@
///***************************************************************************
// Product: DPP example, EFM32-SLSTK3401A board, cooperative QV kernel
// Last Updated for Version: 5.9.0
// Date of the Last Update: 2017-05-09
// Last Updated for Version: 5.9.5
// Date of the Last Update: 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -41,11 +41,11 @@
#include "em_usart.h" // USART (SiLabs)
// add other drivers if necessary...
Q_DEFINE_THIS_FILE
// namespace DPP *************************************************************
namespace DPP {
Q_DEFINE_THIS_FILE
// !!!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
// Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
// DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!

8
examples/arm-cm/dpp_efm32-slstk3401a/qxk/bsp.cpp
View File

@ -1,7 +1,7 @@
///***************************************************************************
// Product: DPP example, EFM32-SLSTK3401A board, preemptive QXK kernel
// Last Updated for Version: 5.9.0
// Date of the Last Update: 2017-05-09
// Last Updated for Version: 5.9.5
// Date of the Last Update: 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -41,11 +41,11 @@
#include "em_usart.h" // USART (SiLabs)
// add other drivers if necessary...
Q_DEFINE_THIS_FILE
// namespace DPP *************************************************************
namespace DPP {
Q_DEFINE_THIS_FILE
// !!!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
// Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
// DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!

8
examples/arm-cm/dpp_efm32-slstk3401a/win32-qv/bsp.cpp
View File

@ -1,7 +1,7 @@
//****************************************************************************
// Product: DPP example, Win32-GUI
// Last updated for version 5.6.5
// Last updated on 2016-05-13
// Last updated for version 5.9.5
// Last updated on 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -47,6 +47,8 @@
#include <winsock2.h> // for Windows network facilities
#endif
Q_DEFINE_THIS_FILE
//****************************************************************************
// thread function for running the application main()
static DWORD WINAPI appThread(LPVOID par) {
@ -57,8 +59,6 @@ static DWORD WINAPI appThread(LPVOID par) {
//****************************************************************************
namespace DPP {
Q_DEFINE_THIS_FILE
// local variables -----------------------------------------------------------
static HINSTANCE l_hInst; // this application instance
static HWND l_hWnd; // main window handle

8
examples/arm-cm/dpp_efm32-slstk3401a/win32/bsp.cpp
View File

@ -1,7 +1,7 @@
//****************************************************************************
// Product: DPP example, Win32-GUI
// Last updated for version 5.6.5
// Last updated on 2016-05-13
// Last updated for version 5.9.5
// Last updated on 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -47,6 +47,8 @@
#include <winsock2.h> // for Windows network facilities
#endif
Q_DEFINE_THIS_FILE
//****************************************************************************
// thread function for running the application main()
static DWORD WINAPI appThread(LPVOID par) {
@ -57,8 +59,6 @@ static DWORD WINAPI appThread(LPVOID par) {
//****************************************************************************
namespace DPP {
Q_DEFINE_THIS_FILE
// local variables -----------------------------------------------------------
static HINSTANCE l_hInst; // this application instance
static HWND l_hWnd; // main window handle

8
examples/arm-cm/dpp_ek-tm4c123gxl/qk/bsp.cpp
View File

@ -1,7 +1,7 @@
///***************************************************************************
// Product: DPP example, EK-TM4C123GXL board, preemptive QK kernel
// Last updated for version 5.9.0
// Last updated on 2017-05-09
// Last updated for version 5.9.5
// Last updated on 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -41,11 +41,11 @@
#include "gpio.h" // GPIO driver (TI)
// add other drivers if necessary...
Q_DEFINE_THIS_FILE
// namespace DPP *************************************************************
namespace DPP {
Q_DEFINE_THIS_FILE
// !!!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
// Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
// DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!

8
examples/arm-cm/dpp_ek-tm4c123gxl/qv/bsp.cpp
View File

@ -1,7 +1,7 @@
///***************************************************************************
// Product: DPP example, EK-TM4C123GXL board, cooperative QV kernel
// Last updated for version 5.9.0
// Last updated on 2017-05-09
// Last updated for version 5.9.5
// Last updated on 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -41,11 +41,11 @@
#include "gpio.h" // GPIO driver (TI)
// add other drivers if necessary...
Q_DEFINE_THIS_FILE
// namespace DPP *************************************************************
namespace DPP {
Q_DEFINE_THIS_FILE
// !!!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
// Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
// DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!

8
examples/arm-cm/dpp_ek-tm4c123gxl/qxk/bsp.cpp
View File

@ -1,7 +1,7 @@
///***************************************************************************
// Product: DPP example, EK-TM4C123GXL board, preemptive QXK kernel
// Last updated for version 5.9.0
// Last updated on 2017-05-09
// Last updated for version 5.9.5
// Last updated on 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -41,11 +41,11 @@
#include "gpio.h" // GPIO driver (TI)
// add other drivers if necessary...
Q_DEFINE_THIS_FILE
// namespace DPP *************************************************************
namespace DPP {
Q_DEFINE_THIS_FILE
// !!!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
// Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
// DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!

8
examples/arm-cm/dpp_mbed-lpc1768/qk/bsp.cpp
View File

@ -1,7 +1,7 @@
///***************************************************************************
// Product: DPP example, NXP mbed-LPC1768 board, preemptive QK kernel
// Last updated for version 5.9.0
// Last updated on 2017-05-09
// Last updated for version 5.9.5
// Last updated on 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -38,11 +38,11 @@
#include "LPC17xx.h" // CMSIS-compliant header file for the MCU used
// add other drivers if necessary...
Q_DEFINE_THIS_FILE
// namespace DPP *************************************************************
namespace DPP {
Q_DEFINE_THIS_FILE
// !!!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
// Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
// DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!

8
examples/arm-cm/dpp_mbed-lpc1768/qv/bsp.cpp
View File

@ -1,7 +1,7 @@
///***************************************************************************
// Product: DPP example, NXP mbed-LPC1768 board, coopearative QV kernel
// Last updated for version 5.9.0
// Last updated on 2017-05-09
// Last updated for version 5.9.5
// Last updated on 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -38,11 +38,11 @@
#include "LPC17xx.h" // CMSIS-compliant header file for the MCU used
// add other drivers if necessary...
Q_DEFINE_THIS_FILE
// namespace DPP *************************************************************
namespace DPP {
Q_DEFINE_THIS_FILE
// !!!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
// Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
// DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!

8
examples/arm-cm/dpp_nucleo-l053r8/qk/bsp.cpp
View File

@ -1,7 +1,7 @@
///***************************************************************************
// Product: DPP example, STM32 NUCLEO-L053R8 board, preemptive QK kernel
// Last updated for version 5.9.0
// Last updated on 2016-05-09
// Last updated for version 5.9.5
// Last updated on 2016-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -38,11 +38,11 @@
#include "stm32l0xx.h" // CMSIS-compliant header file for the MCU used
// add other drivers if necessary...
Q_DEFINE_THIS_FILE
// namespace DPP *************************************************************
namespace DPP {
Q_DEFINE_THIS_FILE
// !!!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
// Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
// DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!

8
examples/arm-cm/dpp_nucleo-l053r8/qv/bsp.cpp
View File

@ -1,7 +1,7 @@
///***************************************************************************
// Product: DPP example, STM32 NUCLEO-L053R8 board, cooperative QV kernel
// Last updated for version 5.9.0
// Last updated on 2017-05-09
// Last updated for version 5.9.5
// Last updated on 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -38,11 +38,11 @@
#include "stm32l0xx.h" // CMSIS-compliant header file for the MCU used
// add other drivers if necessary...
Q_DEFINE_THIS_FILE
// namespace DPP *************************************************************
namespace DPP {
Q_DEFINE_THIS_FILE
// !!!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
// Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
// DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!

8
examples/arm-cm/dpp_nucleo-l053r8/qxk/bsp.cpp
View File

@ -1,7 +1,7 @@
///***************************************************************************
// Product: DPP example, STM32 NUCLEO-L053R8 board, preemptive QXK kernel
// Last updated for version 5.9.0
// Last updated on 2017-05-09
// Last updated for version 5.9.5
// Last updated on 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -38,11 +38,11 @@
#include "stm32l0xx.h" // CMSIS-compliant header file for the MCU used
// add other drivers if necessary...
Q_DEFINE_THIS_FILE
// namespace DPP *************************************************************
namespace DPP {
Q_DEFINE_THIS_FILE
// !!!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
// Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
// DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!

8
examples/arm-cm/dpp_nucleo-l152re/qk/bsp.cpp
View File

@ -1,7 +1,7 @@
///***************************************************************************
// Product: DPP example, STM32 NUCLEO-L152RE board, preemptive QK kernel
// Last updated for version 5.9.0
// Last updated on 2017-05-09
// Last updated for version 5.9.5
// Last updated on 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -38,11 +38,11 @@
#include "stm32l1xx.h" // CMSIS-compliant header file for the MCU used
// add other drivers if necessary...
Q_DEFINE_THIS_FILE
// namespace DPP *************************************************************
namespace DPP {
Q_DEFINE_THIS_FILE
// !!!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
// Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
// DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!

8
examples/arm-cm/dpp_nucleo-l152re/qv/bsp.cpp
View File

@ -1,7 +1,7 @@
///***************************************************************************
// Product: DPP example, STM32 NUCLEO-L152RE board, cooperative QV kernel
// Last updated for version 5.9.0
// Last updated on 2017-05-09
// Last updated for version 5.9.5
// Last updated on 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -38,11 +38,11 @@
#include "stm32l1xx.h" // CMSIS-compliant header file for the MCU used
// add other drivers if necessary...
Q_DEFINE_THIS_FILE
// namespace DPP *************************************************************
namespace DPP {
Q_DEFINE_THIS_FILE
// !!!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
// Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
// DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!

8
examples/arm-cm/dpp_stm32f4-discovery/qk/bsp.cpp
View File

@ -1,7 +1,7 @@
///***************************************************************************
// Product: DPP example, STM32F4-Discovery board, preemptive QK kernel
// Last Updated for Version: 5.9.1
// Date of the Last Update: 2017-06-02
// Last Updated for Version: 5.9.5
// Date of the Last Update: 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -42,11 +42,11 @@
#include "stm32f4xx_usart.h"
// add other drivers if necessary...
Q_DEFINE_THIS_FILE
// namespace DPP *************************************************************
namespace DPP {
Q_DEFINE_THIS_FILE
// !!!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
// Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
// DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!

8
examples/arm-cm/dpp_stm32f4-discovery/qv/bsp.cpp
View File

@ -1,7 +1,7 @@
///***************************************************************************
// Product: DPP example, STM32F4-Discovery board, cooperative QV kernel
// Last Updated for Version: 5.9.1
// Date of the Last Update: 2017-06-02
// Last Updated for Version: 5.9.5
// Date of the Last Update: 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -42,11 +42,11 @@
#include "stm32f4xx_usart.h"
// add other drivers if necessary...
Q_DEFINE_THIS_FILE
// namespace DPP *************************************************************
namespace DPP {
Q_DEFINE_THIS_FILE
// !!!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
// Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
// DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!

8
examples/arm-cm/dpp_stm32f4-discovery/qxk/bsp.cpp
View File

@ -1,7 +1,7 @@
///***************************************************************************
// Product: DPP example, STM32F4-Discovery board, dual-mode QXK kernel
// Last Updated for Version: 5.9.1
// Date of the Last Update: 2017-06-02
// Last Updated for Version: 5.9.5
// Date of the Last Update: 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -42,11 +42,11 @@
#include "stm32f4xx_usart.h"
// add other drivers if necessary...
Q_DEFINE_THIS_FILE
// namespace DPP *************************************************************
namespace DPP {
Q_DEFINE_THIS_FILE
// !!!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
// Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
// DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!

148
examples/arm-cm/dpp_stm32f746g-discovery/qk/arm/DebugConfig/dpp-dbg_STM32F746NGHx_1.0.0.dbgconf
View File

@ -1,148 +0,0 @@
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Debug MCU Configuration
// <o0.0> DBG_SLEEP
// <i> Debug Sleep Mode
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
// <o0.1> DBG_STOP
// <i> Debug Stop Mode
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
// <o0.2> DBG_STANDBY
// <i> Debug Standby Mode
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
// </h>
DbgMCU_CR = 0x00000007;
// <h> Debug MCU APB1 Configuration
// <o0.0> DBG_TIM2_STOP
// <i> TIM2 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.1> DBG_TIM3_STOP
// <i> TIM3 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.2> DBG_TIM4_STOP
// <i> TIM4 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.3> DBG_TIM5_STOP
// <i> TIM5 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.4> DBG_TIM6_STOP
// <i> TIM6 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.5> DBG_TIM7_STOP
// <i> TIM7 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.6> DBG_TIM12_STOP
// <i> TIM12 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.7> DBG_TIM13_STOP
// <i> TIM13 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.8> DBG_TIM14_STOP
// <i> TIM14 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.9> DBG_LPTIM1_STOP
// <i> LPTMI1 counter stopped when core is halted
// <i> 0: The clock of LPTIM1 counter is fed even if the core is halted
// <i> 1: The clock of LPTIM1 counter is stopped when the core is halted
// <o0.10> DBG_RTC_STOP
// <i> RTC stopped when Core is halted
// <i> 0: The RTC counter clock continues even if the core is halted
// <i> 1: The RTC counter clock is stopped when the core is halted
// <o0.11> DBG_WWDG_STOP
// <i> Debug Window Watchdog stopped when Core is halted
// <i> 0: The window watchdog counter clock continues even if the core is halted
// <i> 1: The window watchdog counter clock is stopped when the core is halted
// <o0.12> DBG_IWDG_STOP
// <i> Debug independent watchdog stopped when core is halted
// <i> 0: The independent watchdog counter clock continues even if the core is halted
// <i> 1: The independent watchdog counter clock is stopped when the core is halted
// <o0.21> DBG_I2C1_SMBUS_TIMEOUT
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The SMBUS timeout is frozen
// <o0.22> DBG_I2C2_SMBUS_TIMEOUT
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The SMBUS timeout is frozen
// <o0.23> DBG_I2C3_SMBUS_TIMEOUT
// <i> I2C3 SMBUS timeout mode stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The SMBUS timeout is frozen
// <o0.24> DBG_I2C4_SMBUS_TIMEOUT
// <i> I2C4 SMBUS timeout mode stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The SMBUS timeout is frozen
// <o0.25> DBG_CAN1_STOP
// <i> Debug CAN1 stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The CAN1 receive registers are frozen
// <o0.26> DBG_CAN2_STOP
// <i> Debug CAN2 stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The CAN2 receive registers are frozen
// </h>
DbgMCU_APB1_Fz = 0x00000000;
// <h> Debug MCU APB2 Configuration
// <o0.0> DBG_TIM1_STOP
// <i> TIM1 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.1> DBG_TIM8_STOP
// <i> TIM8 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.16> DBG_TIM9_STOP
// <i> TIM9 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.17> DBG_TIM10_STOP
// <i> TIM10 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.18> DBG_TIM11_STOP
// <i> TIM11 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// </h>
DbgMCU_APB2_Fz = 0x00000000;
// <h> TPIU Pin Routing (TRACECLK fixed on Pin PE2)
// <o0> TRACED0
// <i> ETM Trace Data 0
// <0=> Pin PC1
// <1=> Pin PE3
// <2=> Pin PG13
// <o1> TRACED1
// <i> ETM Trace Data 1
// <0=> Pin PC8
// <1=> Pin PE4
// <2=> Pin PG14
// <o2> TRACED2
// <i> ETM Trace Data 2
// <0=> Pin PD2
// <1=> Pin PE5
// <o3> TRACED3
// <i> ETM Trace Data 3
// <0=> Pin PC12
// <1=> Pin PE6
ETMTrace_D0 = 1;
ETMTrace_D1 = 1;
ETMTrace_D2 = 1;
ETMTrace_D3 = 1;
// </h>
// <<< end of configuration section >>>

148
examples/arm-cm/dpp_stm32f746g-discovery/qk/arm/DebugConfig/dpp-rel_STM32F746NGHx_1.0.0.dbgconf
View File

@ -1,148 +0,0 @@
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Debug MCU Configuration
// <o0.0> DBG_SLEEP
// <i> Debug Sleep Mode
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
// <o0.1> DBG_STOP
// <i> Debug Stop Mode
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
// <o0.2> DBG_STANDBY
// <i> Debug Standby Mode
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
// </h>
DbgMCU_CR = 0x00000007;
// <h> Debug MCU APB1 Configuration
// <o0.0> DBG_TIM2_STOP
// <i> TIM2 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.1> DBG_TIM3_STOP
// <i> TIM3 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.2> DBG_TIM4_STOP
// <i> TIM4 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.3> DBG_TIM5_STOP
// <i> TIM5 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.4> DBG_TIM6_STOP
// <i> TIM6 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.5> DBG_TIM7_STOP
// <i> TIM7 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.6> DBG_TIM12_STOP
// <i> TIM12 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.7> DBG_TIM13_STOP
// <i> TIM13 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.8> DBG_TIM14_STOP
// <i> TIM14 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.9> DBG_LPTIM1_STOP
// <i> LPTMI1 counter stopped when core is halted
// <i> 0: The clock of LPTIM1 counter is fed even if the core is halted
// <i> 1: The clock of LPTIM1 counter is stopped when the core is halted
// <o0.10> DBG_RTC_STOP
// <i> RTC stopped when Core is halted
// <i> 0: The RTC counter clock continues even if the core is halted
// <i> 1: The RTC counter clock is stopped when the core is halted
// <o0.11> DBG_WWDG_STOP
// <i> Debug Window Watchdog stopped when Core is halted
// <i> 0: The window watchdog counter clock continues even if the core is halted
// <i> 1: The window watchdog counter clock is stopped when the core is halted
// <o0.12> DBG_IWDG_STOP
// <i> Debug independent watchdog stopped when core is halted
// <i> 0: The independent watchdog counter clock continues even if the core is halted
// <i> 1: The independent watchdog counter clock is stopped when the core is halted
// <o0.21> DBG_I2C1_SMBUS_TIMEOUT
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The SMBUS timeout is frozen
// <o0.22> DBG_I2C2_SMBUS_TIMEOUT
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The SMBUS timeout is frozen
// <o0.23> DBG_I2C3_SMBUS_TIMEOUT
// <i> I2C3 SMBUS timeout mode stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The SMBUS timeout is frozen
// <o0.24> DBG_I2C4_SMBUS_TIMEOUT
// <i> I2C4 SMBUS timeout mode stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The SMBUS timeout is frozen
// <o0.25> DBG_CAN1_STOP
// <i> Debug CAN1 stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The CAN1 receive registers are frozen
// <o0.26> DBG_CAN2_STOP
// <i> Debug CAN2 stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The CAN2 receive registers are frozen
// </h>
DbgMCU_APB1_Fz = 0x00000000;
// <h> Debug MCU APB2 Configuration
// <o0.0> DBG_TIM1_STOP
// <i> TIM1 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.1> DBG_TIM8_STOP
// <i> TIM8 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.16> DBG_TIM9_STOP
// <i> TIM9 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.17> DBG_TIM10_STOP
// <i> TIM10 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.18> DBG_TIM11_STOP
// <i> TIM11 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// </h>
DbgMCU_APB2_Fz = 0x00000000;
// <h> TPIU Pin Routing (TRACECLK fixed on Pin PE2)
// <o0> TRACED0
// <i> ETM Trace Data 0
// <0=> Pin PC1
// <1=> Pin PE3
// <2=> Pin PG13
// <o1> TRACED1
// <i> ETM Trace Data 1
// <0=> Pin PC8
// <1=> Pin PE4
// <2=> Pin PG14
// <o2> TRACED2
// <i> ETM Trace Data 2
// <0=> Pin PD2
// <1=> Pin PE5
// <o3> TRACED3
// <i> ETM Trace Data 3
// <0=> Pin PC12
// <1=> Pin PE6
ETMTrace_D0 = 1;
ETMTrace_D1 = 1;
ETMTrace_D2 = 1;
ETMTrace_D3 = 1;
// </h>
// <<< end of configuration section >>>

148
examples/arm-cm/dpp_stm32f746g-discovery/qk/arm/DebugConfig/dpp-spy_STM32F746NGHx_1.0.0.dbgconf
View File

@ -1,148 +0,0 @@
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Debug MCU Configuration
// <o0.0> DBG_SLEEP
// <i> Debug Sleep Mode
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
// <o0.1> DBG_STOP
// <i> Debug Stop Mode
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
// <o0.2> DBG_STANDBY
// <i> Debug Standby Mode
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
// </h>
DbgMCU_CR = 0x00000007;
// <h> Debug MCU APB1 Configuration
// <o0.0> DBG_TIM2_STOP
// <i> TIM2 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.1> DBG_TIM3_STOP
// <i> TIM3 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.2> DBG_TIM4_STOP
// <i> TIM4 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.3> DBG_TIM5_STOP
// <i> TIM5 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.4> DBG_TIM6_STOP
// <i> TIM6 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.5> DBG_TIM7_STOP
// <i> TIM7 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.6> DBG_TIM12_STOP
// <i> TIM12 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.7> DBG_TIM13_STOP
// <i> TIM13 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.8> DBG_TIM14_STOP
// <i> TIM14 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.9> DBG_LPTIM1_STOP
// <i> LPTMI1 counter stopped when core is halted
// <i> 0: The clock of LPTIM1 counter is fed even if the core is halted
// <i> 1: The clock of LPTIM1 counter is stopped when the core is halted
// <o0.10> DBG_RTC_STOP
// <i> RTC stopped when Core is halted
// <i> 0: The RTC counter clock continues even if the core is halted
// <i> 1: The RTC counter clock is stopped when the core is halted
// <o0.11> DBG_WWDG_STOP
// <i> Debug Window Watchdog stopped when Core is halted
// <i> 0: The window watchdog counter clock continues even if the core is halted
// <i> 1: The window watchdog counter clock is stopped when the core is halted
// <o0.12> DBG_IWDG_STOP
// <i> Debug independent watchdog stopped when core is halted
// <i> 0: The independent watchdog counter clock continues even if the core is halted
// <i> 1: The independent watchdog counter clock is stopped when the core is halted
// <o0.21> DBG_I2C1_SMBUS_TIMEOUT
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The SMBUS timeout is frozen
// <o0.22> DBG_I2C2_SMBUS_TIMEOUT
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The SMBUS timeout is frozen
// <o0.23> DBG_I2C3_SMBUS_TIMEOUT
// <i> I2C3 SMBUS timeout mode stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The SMBUS timeout is frozen
// <o0.24> DBG_I2C4_SMBUS_TIMEOUT
// <i> I2C4 SMBUS timeout mode stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The SMBUS timeout is frozen
// <o0.25> DBG_CAN1_STOP
// <i> Debug CAN1 stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The CAN1 receive registers are frozen
// <o0.26> DBG_CAN2_STOP
// <i> Debug CAN2 stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The CAN2 receive registers are frozen
// </h>
DbgMCU_APB1_Fz = 0x00000000;
// <h> Debug MCU APB2 Configuration
// <o0.0> DBG_TIM1_STOP
// <i> TIM1 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.1> DBG_TIM8_STOP
// <i> TIM8 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.16> DBG_TIM9_STOP
// <i> TIM9 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.17> DBG_TIM10_STOP
// <i> TIM10 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.18> DBG_TIM11_STOP
// <i> TIM11 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// </h>
DbgMCU_APB2_Fz = 0x00000000;
// <h> TPIU Pin Routing (TRACECLK fixed on Pin PE2)
// <o0> TRACED0
// <i> ETM Trace Data 0
// <0=> Pin PC1
// <1=> Pin PE3
// <2=> Pin PG13
// <o1> TRACED1
// <i> ETM Trace Data 1
// <0=> Pin PC8
// <1=> Pin PE4
// <2=> Pin PG14
// <o2> TRACED2
// <i> ETM Trace Data 2
// <0=> Pin PD2
// <1=> Pin PE5
// <o3> TRACED3
// <i> ETM Trace Data 3
// <0=> Pin PC12
// <1=> Pin PE6
ETMTrace_D0 = 1;
ETMTrace_D1 = 1;
ETMTrace_D2 = 1;
ETMTrace_D3 = 1;
// </h>
// <<< end of configuration section >>>

4
examples/arm-cm/dpp_stm32f746g-discovery/qk/arm/dpp-qk.uvoptx
View File

@ -912,8 +912,8 @@
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\..\3rd_party\stm32f7-discovery\arm\startup_stm32f4xx.s</PathWithFileName>
<FilenameWithoutPath>startup_stm32f4xx.s</FilenameWithoutPath>
<PathWithFileName>..\..\..\..\..\3rd_party\stm32f7-discovery\arm\startup_stm32f746xx.s</PathWithFileName>
<FilenameWithoutPath>startup_stm32f746xx.s</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>

12
examples/arm-cm/dpp_stm32f746g-discovery/qk/arm/dpp-qk.uvprojx
View File

@ -418,9 +418,9 @@
<GroupName>stm32f7-discovery</GroupName>
<Files>
<File>
<FileName>startup_stm32f4xx.s</FileName>
<FileName>startup_stm32f746xx.s</FileName>
<FileType>2</FileType>
<FilePath>..\..\..\..\..\3rd_party\stm32f7-discovery\arm\startup_stm32f4xx.s</FilePath>
<FilePath>..\..\..\..\..\3rd_party\stm32f7-discovery\arm\startup_stm32f746xx.s</FilePath>
</File>
<File>
<FileName>stm32f7xx.h</FileName>
@ -1104,9 +1104,9 @@
<GroupName>stm32f7-discovery</GroupName>
<Files>
<File>
<FileName>startup_stm32f4xx.s</FileName>
<FileName>startup_stm32f746xx.s</FileName>
<FileType>2</FileType>
<FilePath>..\..\..\..\..\3rd_party\stm32f7-discovery\arm\startup_stm32f4xx.s</FilePath>
<FilePath>..\..\..\..\..\3rd_party\stm32f7-discovery\arm\startup_stm32f746xx.s</FilePath>
</File>
<File>
<FileName>stm32f7xx.h</FileName>
@ -1790,9 +1790,9 @@
<GroupName>stm32f7-discovery</GroupName>
<Files>
<File>
<FileName>startup_stm32f4xx.s</FileName>
<FileName>startup_stm32f746xx.s</FileName>
<FileType>2</FileType>
<FilePath>..\..\..\..\..\3rd_party\stm32f7-discovery\arm\startup_stm32f4xx.s</FilePath>
<FilePath>..\..\..\..\..\3rd_party\stm32f7-discovery\arm\startup_stm32f746xx.s</FilePath>
</File>
<File>
<FileName>stm32f7xx.h</FileName>

8
examples/arm-cm/dpp_stm32f746g-discovery/qk/bsp.cpp
View File

@ -1,7 +1,7 @@
///***************************************************************************
// Product: DPP example, STM32746G-Discovery board, preemptive QK kernel
// Last Updated for Version: 5.9.0
// Date of the Last Update: 2017-05-09
// Last Updated for Version: 5.9.5
// Date of the Last Update: 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -40,11 +40,11 @@
#include "stm32746g_discovery.h"
// add other drivers if necessary...
Q_DEFINE_THIS_FILE
// namespace DPP *************************************************************
namespace DPP {
Q_DEFINE_THIS_FILE
// !!!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
// Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
// DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!

6
examples/arm-cm/dpp_stm32f746g-discovery/qk/gnu/Makefile
View File

@ -1,7 +1,7 @@
##############################################################################
# Product: Makefile for DPP on STM32F746G-Discovery, QK kernel, GNU-ARM
# Last Updated for Version: 5.8.2
# Date of the Last Update: 2017-02-04
# Last Updated for Version: 5.9.5
# Date of the Last Update: 2017-07-19
#
# Q u a n t u m L e a P s
# ---------------------------
@ -96,7 +96,7 @@ ASM_SRCS :=
# C source files
C_SRCS := \
startup_stm32f4xx.c \
startup_stm32f746xx.c \
system_stm32f7xx.c \
stm32746g_discovery.c \
stm32f7xx_hal.c \

4
examples/arm-cm/dpp_stm32f746g-discovery/qv/arm/dpp-qv.uvoptx
View File

@ -963,8 +963,8 @@
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\..\3rd_party\stm32f7-discovery\arm\startup_stm32f4xx.s</PathWithFileName>
<FilenameWithoutPath>startup_stm32f4xx.s</FilenameWithoutPath>
<PathWithFileName>..\..\..\..\..\3rd_party\stm32f7-discovery\arm\startup_stm32f746xx.s</PathWithFileName>
<FilenameWithoutPath>startup_stm32f746xx.s</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>

12
examples/arm-cm/dpp_stm32f746g-discovery/qv/arm/dpp-qv.uvprojx
View File

@ -418,9 +418,9 @@
<GroupName>stm32f7-discovery</GroupName>
<Files>
<File>
<FileName>startup_stm32f4xx.s</FileName>
<FileName>startup_stm32f746xx.s</FileName>
<FileType>2</FileType>
<FilePath>..\..\..\..\..\3rd_party\stm32f7-discovery\arm\startup_stm32f4xx.s</FilePath>
<FilePath>..\..\..\..\..\3rd_party\stm32f7-discovery\arm\startup_stm32f746xx.s</FilePath>
</File>
<File>
<FileName>stm32f7xx.h</FileName>
@ -1099,9 +1099,9 @@
<GroupName>stm32f7-discovery</GroupName>
<Files>
<File>
<FileName>startup_stm32f4xx.s</FileName>
<FileName>startup_stm32f746xx.s</FileName>
<FileType>2</FileType>
<FilePath>..\..\..\..\..\3rd_party\stm32f7-discovery\arm\startup_stm32f4xx.s</FilePath>
<FilePath>..\..\..\..\..\3rd_party\stm32f7-discovery\arm\startup_stm32f746xx.s</FilePath>
</File>
<File>
<FileName>stm32f7xx.h</FileName>
@ -1780,9 +1780,9 @@
<GroupName>stm32f7-discovery</GroupName>
<Files>
<File>
<FileName>startup_stm32f4xx.s</FileName>
<FileName>startup_stm32f746xx.s</FileName>
<FileType>2</FileType>
<FilePath>..\..\..\..\..\3rd_party\stm32f7-discovery\arm\startup_stm32f4xx.s</FilePath>
<FilePath>..\..\..\..\..\3rd_party\stm32f7-discovery\arm\startup_stm32f746xx.s</FilePath>
</File>
<File>
<FileName>stm32f7xx.h</FileName>

8
examples/arm-cm/dpp_stm32f746g-discovery/qv/bsp.cpp
View File

@ -1,7 +1,7 @@
///***************************************************************************
// Product: DPP example, STM32746G-Discovery board, cooperative QV kernel
// Last Updated for Version: 5.9.0
// Date of the Last Update: 2017-05-09
// Last Updated for Version: 5.9.5
// Date of the Last Update: 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -40,11 +40,11 @@
#include "stm32746g_discovery.h"
// add other drivers if necessary...
Q_DEFINE_THIS_FILE
// namespace DPP *************************************************************
namespace DPP {
Q_DEFINE_THIS_FILE
// !!!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
// Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
// DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!

6
examples/arm-cm/dpp_stm32f746g-discovery/qv/gnu/Makefile
View File

@ -1,7 +1,7 @@
##############################################################################
# Product: Makefile for DPP on STM32F746G-Discovery, QV kernel, GNU-ARM
# Last Updated for Version: 5.8.2
# Date of the Last Update: 2017-02-04
# Last Updated for Version: 5.9.5
# Date of the Last Update: 2017-07-19
#
# Q u a n t u m L e a P s
# ---------------------------
@ -96,7 +96,7 @@ ASM_SRCS :=
# C source files
C_SRCS := \
startup_stm32f4xx.c \
startup_stm32f746xx.c \
system_stm32f7xx.c \
stm32746g_discovery.c \
stm32f7xx_hal.c \

148
examples/arm-cm/dpp_stm32f746g-discovery/qxk/arm/DebugConfig/dpp-dbg_STM32F746NGHx_1.0.0.dbgconf
View File

@ -1,148 +0,0 @@
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Debug MCU Configuration
// <o0.0> DBG_SLEEP
// <i> Debug Sleep Mode
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
// <o0.1> DBG_STOP
// <i> Debug Stop Mode
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
// <o0.2> DBG_STANDBY
// <i> Debug Standby Mode
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
// </h>
DbgMCU_CR = 0x00000007;
// <h> Debug MCU APB1 Configuration
// <o0.0> DBG_TIM2_STOP
// <i> TIM2 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.1> DBG_TIM3_STOP
// <i> TIM3 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.2> DBG_TIM4_STOP
// <i> TIM4 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.3> DBG_TIM5_STOP
// <i> TIM5 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.4> DBG_TIM6_STOP
// <i> TIM6 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.5> DBG_TIM7_STOP
// <i> TIM7 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.6> DBG_TIM12_STOP
// <i> TIM12 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.7> DBG_TIM13_STOP
// <i> TIM13 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.8> DBG_TIM14_STOP
// <i> TIM14 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.9> DBG_LPTIM1_STOP
// <i> LPTMI1 counter stopped when core is halted
// <i> 0: The clock of LPTIM1 counter is fed even if the core is halted
// <i> 1: The clock of LPTIM1 counter is stopped when the core is halted
// <o0.10> DBG_RTC_STOP
// <i> RTC stopped when Core is halted
// <i> 0: The RTC counter clock continues even if the core is halted
// <i> 1: The RTC counter clock is stopped when the core is halted
// <o0.11> DBG_WWDG_STOP
// <i> Debug Window Watchdog stopped when Core is halted
// <i> 0: The window watchdog counter clock continues even if the core is halted
// <i> 1: The window watchdog counter clock is stopped when the core is halted
// <o0.12> DBG_IWDG_STOP
// <i> Debug independent watchdog stopped when core is halted
// <i> 0: The independent watchdog counter clock continues even if the core is halted
// <i> 1: The independent watchdog counter clock is stopped when the core is halted
// <o0.21> DBG_I2C1_SMBUS_TIMEOUT
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The SMBUS timeout is frozen
// <o0.22> DBG_I2C2_SMBUS_TIMEOUT
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The SMBUS timeout is frozen
// <o0.23> DBG_I2C3_SMBUS_TIMEOUT
// <i> I2C3 SMBUS timeout mode stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The SMBUS timeout is frozen
// <o0.24> DBG_I2C4_SMBUS_TIMEOUT
// <i> I2C4 SMBUS timeout mode stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The SMBUS timeout is frozen
// <o0.25> DBG_CAN1_STOP
// <i> Debug CAN1 stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The CAN1 receive registers are frozen
// <o0.26> DBG_CAN2_STOP
// <i> Debug CAN2 stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The CAN2 receive registers are frozen
// </h>
DbgMCU_APB1_Fz = 0x00000000;
// <h> Debug MCU APB2 Configuration
// <o0.0> DBG_TIM1_STOP
// <i> TIM1 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.1> DBG_TIM8_STOP
// <i> TIM8 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.16> DBG_TIM9_STOP
// <i> TIM9 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.17> DBG_TIM10_STOP
// <i> TIM10 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.18> DBG_TIM11_STOP
// <i> TIM11 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// </h>
DbgMCU_APB2_Fz = 0x00000000;
// <h> TPIU Pin Routing (TRACECLK fixed on Pin PE2)
// <o0> TRACED0
// <i> ETM Trace Data 0
// <0=> Pin PC1
// <1=> Pin PE3
// <2=> Pin PG13
// <o1> TRACED1
// <i> ETM Trace Data 1
// <0=> Pin PC8
// <1=> Pin PE4
// <2=> Pin PG14
// <o2> TRACED2
// <i> ETM Trace Data 2
// <0=> Pin PD2
// <1=> Pin PE5
// <o3> TRACED3
// <i> ETM Trace Data 3
// <0=> Pin PC12
// <1=> Pin PE6
ETMTrace_D0 = 1;
ETMTrace_D1 = 1;
ETMTrace_D2 = 1;
ETMTrace_D3 = 1;
// </h>
// <<< end of configuration section >>>

148
examples/arm-cm/dpp_stm32f746g-discovery/qxk/arm/DebugConfig/dpp-rel_STM32F746NGHx_1.0.0.dbgconf
View File

@ -1,148 +0,0 @@
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Debug MCU Configuration
// <o0.0> DBG_SLEEP
// <i> Debug Sleep Mode
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
// <o0.1> DBG_STOP
// <i> Debug Stop Mode
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
// <o0.2> DBG_STANDBY
// <i> Debug Standby Mode
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
// </h>
DbgMCU_CR = 0x00000007;
// <h> Debug MCU APB1 Configuration
// <o0.0> DBG_TIM2_STOP
// <i> TIM2 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.1> DBG_TIM3_STOP
// <i> TIM3 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.2> DBG_TIM4_STOP
// <i> TIM4 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.3> DBG_TIM5_STOP
// <i> TIM5 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.4> DBG_TIM6_STOP
// <i> TIM6 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.5> DBG_TIM7_STOP
// <i> TIM7 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.6> DBG_TIM12_STOP
// <i> TIM12 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.7> DBG_TIM13_STOP
// <i> TIM13 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.8> DBG_TIM14_STOP
// <i> TIM14 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.9> DBG_LPTIM1_STOP
// <i> LPTMI1 counter stopped when core is halted
// <i> 0: The clock of LPTIM1 counter is fed even if the core is halted
// <i> 1: The clock of LPTIM1 counter is stopped when the core is halted
// <o0.10> DBG_RTC_STOP
// <i> RTC stopped when Core is halted
// <i> 0: The RTC counter clock continues even if the core is halted
// <i> 1: The RTC counter clock is stopped when the core is halted
// <o0.11> DBG_WWDG_STOP
// <i> Debug Window Watchdog stopped when Core is halted
// <i> 0: The window watchdog counter clock continues even if the core is halted
// <i> 1: The window watchdog counter clock is stopped when the core is halted
// <o0.12> DBG_IWDG_STOP
// <i> Debug independent watchdog stopped when core is halted
// <i> 0: The independent watchdog counter clock continues even if the core is halted
// <i> 1: The independent watchdog counter clock is stopped when the core is halted
// <o0.21> DBG_I2C1_SMBUS_TIMEOUT
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The SMBUS timeout is frozen
// <o0.22> DBG_I2C2_SMBUS_TIMEOUT
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The SMBUS timeout is frozen
// <o0.23> DBG_I2C3_SMBUS_TIMEOUT
// <i> I2C3 SMBUS timeout mode stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The SMBUS timeout is frozen
// <o0.24> DBG_I2C4_SMBUS_TIMEOUT
// <i> I2C4 SMBUS timeout mode stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The SMBUS timeout is frozen
// <o0.25> DBG_CAN1_STOP
// <i> Debug CAN1 stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The CAN1 receive registers are frozen
// <o0.26> DBG_CAN2_STOP
// <i> Debug CAN2 stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The CAN2 receive registers are frozen
// </h>
DbgMCU_APB1_Fz = 0x00000000;
// <h> Debug MCU APB2 Configuration
// <o0.0> DBG_TIM1_STOP
// <i> TIM1 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.1> DBG_TIM8_STOP
// <i> TIM8 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.16> DBG_TIM9_STOP
// <i> TIM9 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.17> DBG_TIM10_STOP
// <i> TIM10 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.18> DBG_TIM11_STOP
// <i> TIM11 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// </h>
DbgMCU_APB2_Fz = 0x00000000;
// <h> TPIU Pin Routing (TRACECLK fixed on Pin PE2)
// <o0> TRACED0
// <i> ETM Trace Data 0
// <0=> Pin PC1
// <1=> Pin PE3
// <2=> Pin PG13
// <o1> TRACED1
// <i> ETM Trace Data 1
// <0=> Pin PC8
// <1=> Pin PE4
// <2=> Pin PG14
// <o2> TRACED2
// <i> ETM Trace Data 2
// <0=> Pin PD2
// <1=> Pin PE5
// <o3> TRACED3
// <i> ETM Trace Data 3
// <0=> Pin PC12
// <1=> Pin PE6
ETMTrace_D0 = 1;
ETMTrace_D1 = 1;
ETMTrace_D2 = 1;
ETMTrace_D3 = 1;
// </h>
// <<< end of configuration section >>>

148
examples/arm-cm/dpp_stm32f746g-discovery/qxk/arm/DebugConfig/dpp-spy_STM32F746NGHx_1.0.0.dbgconf
View File

@ -1,148 +0,0 @@
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Debug MCU Configuration
// <o0.0> DBG_SLEEP
// <i> Debug Sleep Mode
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
// <o0.1> DBG_STOP
// <i> Debug Stop Mode
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
// <o0.2> DBG_STANDBY
// <i> Debug Standby Mode
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
// </h>
DbgMCU_CR = 0x00000007;
// <h> Debug MCU APB1 Configuration
// <o0.0> DBG_TIM2_STOP
// <i> TIM2 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.1> DBG_TIM3_STOP
// <i> TIM3 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.2> DBG_TIM4_STOP
// <i> TIM4 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.3> DBG_TIM5_STOP
// <i> TIM5 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.4> DBG_TIM6_STOP
// <i> TIM6 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.5> DBG_TIM7_STOP
// <i> TIM7 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.6> DBG_TIM12_STOP
// <i> TIM12 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.7> DBG_TIM13_STOP
// <i> TIM13 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.8> DBG_TIM14_STOP
// <i> TIM14 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.9> DBG_LPTIM1_STOP
// <i> LPTMI1 counter stopped when core is halted
// <i> 0: The clock of LPTIM1 counter is fed even if the core is halted
// <i> 1: The clock of LPTIM1 counter is stopped when the core is halted
// <o0.10> DBG_RTC_STOP
// <i> RTC stopped when Core is halted
// <i> 0: The RTC counter clock continues even if the core is halted
// <i> 1: The RTC counter clock is stopped when the core is halted
// <o0.11> DBG_WWDG_STOP
// <i> Debug Window Watchdog stopped when Core is halted
// <i> 0: The window watchdog counter clock continues even if the core is halted
// <i> 1: The window watchdog counter clock is stopped when the core is halted
// <o0.12> DBG_IWDG_STOP
// <i> Debug independent watchdog stopped when core is halted
// <i> 0: The independent watchdog counter clock continues even if the core is halted
// <i> 1: The independent watchdog counter clock is stopped when the core is halted
// <o0.21> DBG_I2C1_SMBUS_TIMEOUT
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The SMBUS timeout is frozen
// <o0.22> DBG_I2C2_SMBUS_TIMEOUT
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The SMBUS timeout is frozen
// <o0.23> DBG_I2C3_SMBUS_TIMEOUT
// <i> I2C3 SMBUS timeout mode stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The SMBUS timeout is frozen
// <o0.24> DBG_I2C4_SMBUS_TIMEOUT
// <i> I2C4 SMBUS timeout mode stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The SMBUS timeout is frozen
// <o0.25> DBG_CAN1_STOP
// <i> Debug CAN1 stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The CAN1 receive registers are frozen
// <o0.26> DBG_CAN2_STOP
// <i> Debug CAN2 stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The CAN2 receive registers are frozen
// </h>
DbgMCU_APB1_Fz = 0x00000000;
// <h> Debug MCU APB2 Configuration
// <o0.0> DBG_TIM1_STOP
// <i> TIM1 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.1> DBG_TIM8_STOP
// <i> TIM8 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.16> DBG_TIM9_STOP
// <i> TIM9 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.17> DBG_TIM10_STOP
// <i> TIM10 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.18> DBG_TIM11_STOP
// <i> TIM11 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// </h>
DbgMCU_APB2_Fz = 0x00000000;
// <h> TPIU Pin Routing (TRACECLK fixed on Pin PE2)
// <o0> TRACED0
// <i> ETM Trace Data 0
// <0=> Pin PC1
// <1=> Pin PE3
// <2=> Pin PG13
// <o1> TRACED1
// <i> ETM Trace Data 1
// <0=> Pin PC8
// <1=> Pin PE4
// <2=> Pin PG14
// <o2> TRACED2
// <i> ETM Trace Data 2
// <0=> Pin PD2
// <1=> Pin PE5
// <o3> TRACED3
// <i> ETM Trace Data 3
// <0=> Pin PC12
// <1=> Pin PE6
ETMTrace_D0 = 1;
ETMTrace_D1 = 1;
ETMTrace_D2 = 1;
ETMTrace_D3 = 1;
// </h>
// <<< end of configuration section >>>

4
examples/arm-cm/dpp_stm32f746g-discovery/qxk/arm/dpp-qxk.uvoptx
View File

@ -924,8 +924,8 @@
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\..\3rd_party\stm32f7-discovery\arm\startup_stm32f4xx.s</PathWithFileName>
<FilenameWithoutPath>startup_stm32f4xx.s</FilenameWithoutPath>
<PathWithFileName>..\..\..\..\..\3rd_party\stm32f7-discovery\arm\startup_stm32f746xx.s</PathWithFileName>
<FilenameWithoutPath>startup_stm32f746xx.s</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>

12
examples/arm-cm/dpp_stm32f746g-discovery/qxk/arm/dpp-qxk.uvprojx
View File

@ -423,9 +423,9 @@
<GroupName>stm32f7-discovery</GroupName>
<Files>
<File>
<FileName>startup_stm32f4xx.s</FileName>
<FileName>startup_stm32f746xx.s</FileName>
<FileType>2</FileType>
<FilePath>..\..\..\..\..\3rd_party\stm32f7-discovery\arm\startup_stm32f4xx.s</FilePath>
<FilePath>..\..\..\..\..\3rd_party\stm32f7-discovery\arm\startup_stm32f746xx.s</FilePath>
</File>
<File>
<FileName>stm32f7xx.h</FileName>
@ -1124,9 +1124,9 @@
<GroupName>stm32f7-discovery</GroupName>
<Files>
<File>
<FileName>startup_stm32f4xx.s</FileName>
<FileName>startup_stm32f746xx.s</FileName>
<FileType>2</FileType>
<FilePath>..\..\..\..\..\3rd_party\stm32f7-discovery\arm\startup_stm32f4xx.s</FilePath>
<FilePath>..\..\..\..\..\3rd_party\stm32f7-discovery\arm\startup_stm32f746xx.s</FilePath>
</File>
<File>
<FileName>stm32f7xx.h</FileName>
@ -1825,9 +1825,9 @@
<GroupName>stm32f7-discovery</GroupName>
<Files>
<File>
<FileName>startup_stm32f4xx.s</FileName>
<FileName>startup_stm32f746xx.s</FileName>
<FileType>2</FileType>
<FilePath>..\..\..\..\..\3rd_party\stm32f7-discovery\arm\startup_stm32f4xx.s</FilePath>
<FilePath>..\..\..\..\..\3rd_party\stm32f7-discovery\arm\startup_stm32f746xx.s</FilePath>
</File>
<File>
<FileName>stm32f7xx.h</FileName>

8
examples/arm-cm/dpp_stm32f746g-discovery/qxk/bsp.cpp
View File

@ -1,7 +1,7 @@
///***************************************************************************
// Product: DPP example, STM32746G-Discovery board, dual-mode QXK kernel
// Last Updated for Version: 5.9.0
// Date of the Last Update: 2017-05-09
// Last Updated for Version: 5.9.5
// Date of the Last Update: 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -40,11 +40,11 @@
#include "stm32746g_discovery.h"
// add other drivers if necessary...
Q_DEFINE_THIS_FILE
// namespace DPP *************************************************************
namespace DPP {
Q_DEFINE_THIS_FILE
// !!!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
// Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
// DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!

6
examples/arm-cm/dpp_stm32f746g-discovery/qxk/gnu/Makefile
View File

@ -1,7 +1,7 @@
##############################################################################
# Product: Makefile for DPP on STM32F746G-Discovery, QXK kernel, GNU-ARM
# Last Updated for Version: 5.8.2
# Date of the Last Update: 2017-02-04
# Last Updated for Version: 5.9.5
# Date of the Last Update: 2017-07-19
#
# Q u a n t u m L e a P s
# ---------------------------
@ -96,7 +96,7 @@ ASM_SRCS :=
# C source files
C_SRCS := \
startup_stm32f4xx.c \
startup_stm32f746xx.c \
system_stm32f7xx.c \
stm32746g_discovery.c \
stm32f7xx_hal.c \

8
examples/arm-cm/game_efm32-slstk3401a/qk/bsp.cpp
View File

@ -1,7 +1,7 @@
///***************************************************************************
// Product: "Fly 'n' Shoot" game example, EFM32-SLSTK3401A board, QK kernel
// Last Updated for Version: 5.9.0
// Date of the Last Update: 2017-05-09
// Last Updated for Version: 5.9.5
// Date of the Last Update: 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -42,11 +42,11 @@
#include "display_ls013b7dh03.h" // LS013b7DH03 display (SiLabs/QL)
// add other drivers if necessary...
Q_DEFINE_THIS_FILE
// namespace GAME ************************************************************
namespace GAME {
Q_DEFINE_THIS_FILE
// !!!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
// Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
// DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!

8
examples/arm-cm/game_efm32-slstk3401a/qv/bsp.cpp
View File

@ -1,7 +1,7 @@
///***************************************************************************
// Product: "Fly 'n' Shoot" game example, EFM32-SLSTK3401A board, QV kernel
// Last Updated for Version: 5.9.0
// Date of the Last Update: 2017-05-09
// Last Updated for Version: 5.9.5
// Date of the Last Update: 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -42,11 +42,11 @@
#include "display_ls013b7dh03.h" // LS013b7DH03 display (SiLabs/QL)
// add other drivers if necessary...
Q_DEFINE_THIS_FILE
// namespace GAME ************************************************************
namespace GAME {
Q_DEFINE_THIS_FILE
// !!!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
// Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
// DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!

8
examples/arm-cm/game_efm32-slstk3401a/win32-qv/bsp.cpp
View File

@ -1,7 +1,7 @@
///***************************************************************************
// Product: "Fly 'n' Shoot" game example for Win32-GUI
// Last updated for version 5.9.0
// Last updated on 2017-05-09
// Last updated for version 5.9.5
// Last updated on 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -47,6 +47,8 @@
#include <winsock2.h> // for Windows network facilities
#endif
Q_DEFINE_THIS_FILE
///***************************************************************************
// thread function for running the application main()
static DWORD WINAPI appThread(LPVOID par) {
@ -57,8 +59,6 @@ static DWORD WINAPI appThread(LPVOID par) {
///***************************************************************************
namespace GAME {
Q_DEFINE_THIS_FILE
// local variables -----------------------------------------------------------
static HINSTANCE l_hInst; // this application instance
static HWND l_hWnd; // main window handle

8
examples/arm-cm/game_efm32-slstk3401a/win32/bsp.cpp
View File

@ -1,7 +1,7 @@
///***************************************************************************
// Product: "Fly 'n' Shoot" game example for Win32-GUI
// Last updated for version 5.9.0
// Last updated on 2017-05-09
// Last updated for version 5.9.5
// Last updated on 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -47,6 +47,8 @@
#include <winsock2.h> // for Windows network facilities
#endif
Q_DEFINE_THIS_FILE
///***************************************************************************
// thread function for running the application main()
static DWORD WINAPI appThread(LPVOID par) {
@ -57,8 +59,6 @@ static DWORD WINAPI appThread(LPVOID par) {
///***************************************************************************
namespace GAME {
Q_DEFINE_THIS_FILE
// local variables -----------------------------------------------------------
static HINSTANCE l_hInst; // this application instance
static HWND l_hWnd; // main window handle

8
examples/arm-cr/dpp_launchxl2-tms57012/qk/bsp.cpp
View File

@ -1,7 +1,7 @@
///***************************************************************************
// Product: DPP example, LAUCHXL2-TMS570LS12 board, preemptive QK kernel
// Last Updated for Version: 5.9.0
// Date of the Last Update: 2017-05-09
// Last Updated for Version: 5.9.5
// Date of the Last Update: 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -45,11 +45,11 @@
#include "sci.h"
// add other drivers if necessary...
Q_DEFINE_THIS_FILE
// namespace DPP *************************************************************
namespace DPP {
Q_DEFINE_THIS_FILE
// Local-scope objects -------------------------------------------------------
#define LED2_PIN 1
#define LED2_PORT gioPORTB

8
examples/arm-cr/dpp_launchxl2-tms57012/qv/bsp.cpp
View File

@ -1,7 +1,7 @@
///***************************************************************************
// Product: DPP example, LAUCHXL2-TMS570LS12 board, cooperative QV kernel
// Last Updated for Version: 5.9.0
// Date of the Last Update: 2017-05-09
// Last Updated for Version: 5.9.5
// Date of the Last Update: 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -45,11 +45,11 @@
#include "sci.h"
// add other drivers if necessary...
Q_DEFINE_THIS_FILE
// namespace DPP *************************************************************
namespace DPP {
Q_DEFINE_THIS_FILE
// Local-scope objects -------------------------------------------------------
#define LED2_PIN 1
#define LED2_PORT gioPORTB

8
examples/arm7-9/dpp_at91sam7s-ek/qk/iar/bsp.cpp
View File

@ -1,7 +1,7 @@
//****************************************************************************
// Product: DPP on AT91SAM7S-EK, preemptive QK kernel, IAR-ARM toolset
// Last Updated for Version: 5.9.0
// Date of the Last Update: 2017-05-09
// Last Updated for Version: 5.9.5
// Date of the Last Update: 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -41,6 +41,8 @@
#pragma diag_suppress=Ta022 // possible ROM access <ptr> from __ramfunc
#pragma diag_suppress=Ta023 // call to non __ramfunc from __ramfunc
Q_DEFINE_THIS_FILE
// extern "C" functions in C =================================================
extern "C" {
//............................................................................
@ -60,8 +62,6 @@ void BSP_irq(void) {
namespace DPP {
Q_DEFINE_THIS_FILE
// Local objects -------------------------------------------------------------
typedef void (*IntVector)(void); // IntVector pointer-to-function

8
examples/arm7-9/dpp_at91sam7s-ek/qv/iar/bsp.cpp
View File

@ -1,7 +1,7 @@
//****************************************************************************
// Product: DPP on AT91SAM7S-EK, cooperative QV kernel, IAR-ARM toolset
// Last Updated for Version: 5.9.0
// Date of the Last Update: 2017-05-09
// Last Updated for Version: 5.9.5
// Date of the Last Update: 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -41,6 +41,8 @@
#pragma diag_suppress=Ta022 // possible ROM access <ptr> from __ramfunc
#pragma diag_suppress=Ta023 // call to non __ramfunc from __ramfunc
Q_DEFINE_THIS_FILE
// extern "C" functions in C =================================================
extern "C" {
//............................................................................
@ -60,8 +62,6 @@ void BSP_irq(void) {
namespace DPP {
Q_DEFINE_THIS_FILE
// Local objects -------------------------------------------------------------
typedef void (*IntVector)(void); // IntVector pointer-to-function

8
examples/embos/arm-cm/dpp_stm32f429-discovery/bsp.cpp
View File

@ -1,7 +1,7 @@
//****************************************************************************
// Product: DPP example, STM32F4-Discovery board, embOS kernel
// Last updated for version 5.9.0
// Last updated on 2017-05-09
// Last updated for version 5.9.5
// Last updated on 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -42,11 +42,11 @@
#include "stm32f4xx_usart.h"
// add other drivers if necessary...
Q_DEFINE_THIS_FILE
// namespace DPP *************************************************************
namespace DPP {
Q_DEFINE_THIS_FILE
// Local-scope objects -------------------------------------------------------
#define LED_GPIO_PORT GPIOD
#define LED_GPIO_CLK RCC_AHB1Periph_GPIOD

8
examples/msp430/dpp_msp-exp430g2/qk/bsp.cpp
View File

@ -1,7 +1,7 @@
//****************************************************************************
// Product: DPP example on MSP-EXP430G2 board, preemptive QK kernel
// Last updated for version 5.9.0
// Last updated on 2017-05-09
// Last updated for version 5.9.5
// Last updated on 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -38,11 +38,11 @@
#include <msp430g2553.h> // MSP430 variant used
// add other drivers if necessary...
Q_DEFINE_THIS_FILE
// namespace DPP *************************************************************
namespace DPP {
Q_DEFINE_THIS_FILE
// Local-scope objects -------------------------------------------------------
// 8MHz clock setting, see BSP::init()
#define BSP_MCK 8000000U

8
examples/msp430/dpp_msp-exp430g2/qv/bsp.cpp
View File

@ -1,7 +1,7 @@
//****************************************************************************
// Product: DPP example on MSP-EXP430G2 board, cooperative QV kernel
// Last updated for version 5.9.0
// Last updated on 2017-05-09
// Last updated for version 5.9.5
// Last updated on 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -38,11 +38,11 @@
#include <msp430g2553.h> // MSP430 variant used
// add other drivers if necessary...
Q_DEFINE_THIS_FILE
// namespace DPP *************************************************************
namespace DPP {
Q_DEFINE_THIS_FILE
// Local-scope objects -------------------------------------------------------
// 8MHz clock setting, see BSP::init()
#define BSP_MCK 8000000U

8
examples/performance/dpp_efm32-slstk3401a/qk/bsp.cpp
View File

@ -1,7 +1,7 @@
///***************************************************************************
// Product: DPP example, EFM32-SLSTK3401A board, preemptive QK kernel
// Last Updated for Version: 5.9.0
// Date of the Last Update: 2017-05-09
// Last Updated for Version: 5.9.5
// Date of the Last Update: 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -41,11 +41,11 @@
#include "em_usart.h" // USART (SiLabs)
// add other drivers if necessary...
Q_DEFINE_THIS_FILE
// namespace DPP *************************************************************
namespace DPP {
Q_DEFINE_THIS_FILE
// !!!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
// Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
// DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!

8
examples/performance/dpp_efm32-slstk3401a/qv/bsp.cpp
View File

@ -1,7 +1,7 @@
///***************************************************************************
// Product: DPP example, EFM32-SLSTK3401A board, cooperative QV kernel
// Last Updated for Version: 5.9.0
// Date of the Last Update: 2017-05-09
// Last Updated for Version: 5.9.5
// Date of the Last Update: 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -41,11 +41,11 @@
#include "em_usart.h" // USART (SiLabs)
// add other drivers if necessary...
Q_DEFINE_THIS_FILE
// namespace DPP *************************************************************
namespace DPP {
Q_DEFINE_THIS_FILE
// !!!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
// Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
// DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!

8
examples/performance/dpp_efm32-slstk3401a/qxk/bsp.cpp
View File

@ -1,7 +1,7 @@
///***************************************************************************
// Product: DPP example, EFM32-SLSTK3401A board, preemptive QXK kernel
// Last Updated for Version: 5.9.0
// Date of the Last Update: 2017-05-09
// Last Updated for Version: 5.9.5
// Date of the Last Update: 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -42,11 +42,11 @@
#include "em_usart.h" // USART (SiLabs)
// add other drivers if necessary...
Q_DEFINE_THIS_FILE
// namespace DPP *************************************************************
namespace DPP {
Q_DEFINE_THIS_FILE
// !!!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
// Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
// DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!

8
examples/performance/dpp_efm32-slstk3401a/ucos-ii/bsp.cpp
View File

@ -1,7 +1,7 @@
///***************************************************************************
// Product: DPP example, EFM32-SLSTK3401A board, uC/OS-II kernel
// Last Updated for Version: 5.9.0
// Date of the Last Update: 2017-05-09
// Last Updated for Version: 5.9.5
// Date of the Last Update: 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -42,11 +42,11 @@
#include "em_usart.h" // USART (SiLabs)
// add other drivers if necessary...
Q_DEFINE_THIS_FILE
// namespace DPP *************************************************************
namespace DPP {
Q_DEFINE_THIS_FILE
// Local-scope objects -------------------------------------------------------
#define LED_PORT gpioPortF
#define LED0_PIN 4

8
examples/posix/dpp/bsp.cpp
View File

@ -1,7 +1,7 @@
//****************************************************************************
// Product: DPP example, POSIX
// Last Updated for Version: 5.9.0
// Date of the Last Update: 2017-05-09
// Last Updated for Version: 5.9.5
// Date of the Last Update: 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -42,11 +42,11 @@
#include <termios.h>
#include <unistd.h>
Q_DEFINE_THIS_FILE
//****************************************************************************
namespace DPP {
Q_DEFINE_THIS_FILE
// Local objects -------------------------------------------------------------
static uint32_t l_rnd; // random seed

8
examples/qutest/dpp/bsp.cpp
View File

@ -1,7 +1,7 @@
//****************************************************************************
// Product: DPP example, QUTEST
// Last Updated for Version: 5.9.0
// Date of the Last Update: 2017-05-10
// Last Updated for Version: 5.9.5
// Date of the Last Update: 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -35,11 +35,11 @@
#include "dpp.h"
#include "bsp.h"
Q_DEFINE_THIS_MODULE("bsp")
// namespace DPP *************************************************************
namespace DPP {
Q_DEFINE_THIS_MODULE("bsp")
static uint32_t l_rnd; // random seed
// BSP functions =============================================================

8
examples/ti-rtos/arm-cm/dpp_ek-tm4c123gxl/bsp.cpp
View File

@ -1,7 +1,7 @@
///***************************************************************************
// Product: DPP example, EK-TM4C123GXL board, TI-RTOS kernel (SYS/BIOS)
// Last updated for version 5.7.3
// Last updated on 2016-10-06
// Last updated for version 5.9.5
// Last updated on 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -40,6 +40,8 @@
#include "ti/drivers/GPIO.h" // GPIO driver (TI)
// add other drivers if necessary...
Q_DEFINE_THIS_FILE
// TI-RTOS callback functions ================================================
extern "C" {
@ -100,8 +102,6 @@ void myIdleFunc() {
// namespace DPP *************************************************************
namespace DPP {
Q_DEFINE_THIS_FILE
// Local-scope objects -------------------------------------------------------
static uint32_t l_rnd; // random seed

8
examples/ucos-ii/arm-cm/dpp_efm32-slstk3401a/bsp.cpp
View File

@ -1,7 +1,7 @@
///***************************************************************************
// Product: DPP example, EFM32-SLSTK3401A board, uC/OS-II kernel
// Last Updated for Version: 5.9.0
// Date of the Last Update: 2017-05-09
// Last Updated for Version: 5.9.5
// Date of the Last Update: 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -41,11 +41,11 @@
#include "em_usart.h" // USART (SiLabs)
// add other drivers if necessary...
Q_DEFINE_THIS_FILE
// namespace DPP *************************************************************
namespace DPP {
Q_DEFINE_THIS_FILE
// Local-scope objects -------------------------------------------------------
#define LED_PORT gpioPortF
#define LED0_PIN 4

8
examples/ucos-ii/arm-cm/dpp_ek-tm4c123gxl/bsp.cpp
View File

@ -1,7 +1,7 @@
///***************************************************************************
// Product: DPP example, EK-TM4C123GXL board, uC/OS-II kernel
// Last updated for version 5.9.0
// Last updated on 2017-05-09
// Last updated for version 5.9.5
// Last updated on 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -41,11 +41,11 @@
#include "gpio.h" // GPIO driver (TI)
// add other drivers if necessary...
Q_DEFINE_THIS_FILE
// namespace DPP *************************************************************
namespace DPP {
Q_DEFINE_THIS_FILE
// Local-scope objects -------------------------------------------------------
#define LED_RED (1U << 1)
#define LED_GREEN (1U << 3)

8
examples/ucos-ii/arm-cm/dpp_nucleo-l152re/bsp.cpp
View File

@ -1,7 +1,7 @@
//****************************************************************************
// Product: DPP example, STM32 NUCLEO-L152RE board, uC/OS-II kernel
// Last updated for version 5.9.0
// Last updated on 2017-05-09
// Last updated for version 5.9.5
// Last updated on 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -38,11 +38,11 @@
#include "stm32l1xx.h" // CMSIS-compliant header file for the MCU used
// add other drivers if necessary...
Q_DEFINE_THIS_FILE
// namespace DPP *************************************************************
namespace DPP {
Q_DEFINE_THIS_FILE
// Local-scope objects -------------------------------------------------------
// LED pins available on the board (just one LED)
#define LED_LD2 (1U << 5)

7
examples/win32-qv/dpp/bsp.cpp
View File

@ -1,7 +1,7 @@
//****************************************************************************
// Product: DPP example (console)
// Last Updated for Version: 5.8.0
// Date of the Last Update: 2016-11-30
// Last Updated for Version: 5.9.5
// Date of the Last Update: 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -46,12 +46,11 @@
#include "qspy.h" // QSPY interface
#endif
Q_DEFINE_THIS_FILE
//****************************************************************************
namespace DPP {
Q_DEFINE_THIS_FILE
// local variables -----------------------------------------------------------
static uint32_t l_rnd; // random seed

7
examples/win32/dpp/bsp.cpp
View File

@ -1,7 +1,7 @@
//****************************************************************************
// Product: DPP example (console)
// Last Updated for Version: 5.8.0
// Date of the Last Update: 2016-11-30
// Last Updated for Version: 5.9.5
// Date of the Last Update: 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
@ -46,12 +46,11 @@
#include "qspy.h" // QSPY interface
#endif
Q_DEFINE_THIS_FILE
//****************************************************************************
namespace DPP {
Q_DEFINE_THIS_FILE
// local variables -----------------------------------------------------------
static uint32_t l_rnd; // random seed

10
include/qassert.h
View File

@ -3,8 +3,8 @@
* @brief Customizable and memory-efficient assertions for embedded systems
* @cond
******************************************************************************
* Last updated for version 5.6.0
* Last updated on 2015-12-18
* Last updated for version 5.9.5
* Last updated on 2017-07-19
*
* Q u a n t u m L e a P s
* ---------------------------
@ -59,6 +59,12 @@
#define Q_ALLEGE_ID(id_, test_) ((void)(test_))
#define Q_ERROR() ((void)0)
#define Q_ERROR_ID(id_) ((void)0)
#define Q_REQUIRE(test_) ((void)0)
#define Q_REQUIRE_ID(id_, test_) ((void)0)
#define Q_ENSURE(test_) ((void)0)
#define Q_ENSURE_ID(id_, test_) ((void)0)
#define Q_INVARIANT(test_) ((void)0)
#define Q_INVARIANT_ID(id_, test_) ((void)0)
#else /* Q_NASSERT not defined--assertion checking enabled */

12
include/qep.h
View File

@ -3,8 +3,8 @@
/// @ingroup qep
/// @cond
///***************************************************************************
/// Last updated for version 5.9.4
/// Last updated on 2017-07-05
/// Last updated for version 5.9.5
/// Last updated on 2017-07-19
///
/// Q u a n t u m L e a P s
/// ---------------------------
@ -43,15 +43,15 @@
//! The current QP version as a decimal constant XYZ, where X is a 1-digit
// major version number, Y is a 1-digit minor version number, and Z is
// a 1-digit release number.
#define QP_VERSION 594
#define QP_VERSION 595
//! The current QP version number string of the form X.Y.Z, where X is
// a 1-digit major version number, Y is a 1-digit minor version number,
// and Z is a 1-digit release number.
#define QP_VERSION_STR "5.9.4"
#define QP_VERSION_STR "5.9.5"
//! Tamperproof current QP release (5.9.4) and date (2017-07-07)
#define QP_RELEASE 0x9A402B7DU
//! Tamperproof current QP release (5.9.5) and date (2017-07-20)
#define QP_RELEASE 0x9A3E2FACU
//****************************************************************************
#ifndef Q_SIGNAL_SIZE

7
include/qpcpp.lnt
View File

@ -1,7 +1,7 @@
//////////////////////////////////////////////////////////////////////////////
// Product: PC-Lint 9.x option file for linting QP/C++ applications
// Last updated for version 5.9.4
// Last updated on 2017-07-05
// Last updated for version 5.9.5
// Last updated on 2017-07-19
//
// Q u a n t u m L e a P s
// ---------------------------
@ -75,7 +75,8 @@
// Assertions
-esym(1960, // Rule 7-3-1, Global declaration of symbol
Q_onAssert,
Q_onTestAssert)
Q_onTestAssert,
Q_this_module_)
-emacro(944, // 0-1-1/2/9 operator ? always evaluates to True
Q_ASSERT_COMPILE)
-emacro(948, // 0-1-9 Operator '==' always evaluates to True

11
src/qxk/qxk.cpp
View File

@ -4,8 +4,8 @@
/// @ingroup qxk
/// @cond
///***************************************************************************
/// Last updated for version 5.9.4
/// Last updated on 2017-07-06
/// Last updated for version 5.9.5
/// Last updated on 2017-07-19
///
/// Q u a n t u m L e a P s
/// ---------------------------
@ -52,6 +52,8 @@
#error "Source file included in a project NOT based on the QXK kernel"
#endif // qxk_h
Q_DEFINE_THIS_MODULE("qxk")
// Public-scope objects ******************************************************
extern "C" {
QXK_Attr QXK_attr_; // global attributes of the QXK kernel
@ -59,8 +61,6 @@ extern "C" {
namespace QP {
Q_DEFINE_THIS_MODULE("qxk")
// Local-scope objects *******************************************************
class QXKIdleThread : public QActive {
public:
@ -443,6 +443,9 @@ QP::QActive *QXK_current(void) {
curr = QXK_attr_.curr;
QF_CRIT_EXIT_();
//! @post the current thread must be valid
Q_ENSURE_ID(900, curr != static_cast<QP::QActive *>(0));
return curr;
}

2
version-5.9.4
View File

@ -1,2 +0,0 @@
QP/C++ 5.9.4
2017-07-07

2
version-5.9.5 Normal file
View File

@ -0,0 +1,2 @@
QP/C++ 5.9.5
2017-07-20