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5.5.1a

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Quantum Leaps 2015-11-09 12:51:39 -05:00
parent a01a83f822
commit 827a825a6c
41 changed files with 2820 additions and 37 deletions
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2
3rd_party/CMSIS-RTX/README.txt vendored
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@ -1,5 +1,5 @@
This folder contains the API, source, and libraries of This folder contains the API, source, and libraries of
CMSIS-RTOS RTX V4.78. CMSIS-RTOS RTX V4.79.
The code in this folder has been taken from the CMSIS distribution: The code in this folder has been taken from the CMSIS distribution:

34
3rd_party/CMSIS/Include/cmsis_ccs.h vendored
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@ -37,40 +37,6 @@
#ifndef CMSIS_CCS_H_ #ifndef CMSIS_CCS_H_
#define CMSIS_CCS_H_ #define CMSIS_CCS_H_
//*****************************************************************************
// CMSIS-compatible instruction calls
//*****************************************************************************
// No Operation
__attribute__( ( always_inline ) ) static inline void __nop(void)
{
__asm(" nop");
}
// Wait For Interrupt
__attribute__( ( always_inline ) ) static inline void __wfi(void)
{
__asm(" wfi");
}
// Wait For Event
__attribute__( ( always_inline ) ) static inline void __wfe(void)
{
__asm(" wfe");
}
// Enable Interrupts
__attribute__( ( always_inline ) ) static inline void __enable_irq(void)
{
__asm(" cpsie i");
}
// Disable Interrupts
__attribute__( ( always_inline ) ) static inline void __disable_irq(void)
{
__asm(" cpsid i");
}
// Data Synchronization Barrier // Data Synchronization Barrier
__attribute__( ( always_inline ) ) static inline void __DSB(void) __attribute__( ( always_inline ) ) static inline void __DSB(void)
{ {

15
examples/arm-cm/dpp_ek-tm4c123gxl/qk/ti/.ccsproject Normal file
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@ -0,0 +1,15 @@
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<isTargetManual value="false"/>
</projectOptions>

296
examples/arm-cm/dpp_ek-tm4c123gxl/qk/ti/.cproject Normal file
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@ -0,0 +1,296 @@
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29
examples/arm-cm/dpp_ek-tm4c123gxl/qk/ti/.launches/dpp-qk.launch Normal file
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/* File: startup_TM4C123GH6PM.c
* Purpose: startup file for TM4C123GH6PM Cortex-M4 device.
* Should be used with TI CCS-ARM Compiler
* Version: CMSIS 4.3.0
* Date: 5 October 2015
*
* Created from the CMSIS template for the specified device
* Quantum Leaps, www.state-machine.com
*
* NOTE:
* The function assert_failed defined at the end of this file defines
* the error/assertion handling policy for the application and might
* need to be customized for each project. This function is defined in
* assembly to re-set the stack pointer, in case it is corrupted by the
* time assert_failed is called.
*/
//****************************************************************************
//
// Startup code for use with TI's Code Composer Studio.
//
// Copyright (c) 2011-2014 Texas Instruments Inc. All rights reserved.
// Software License Agreement
//
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
//****************************************************************************
/* top of stack defined in the linker script -------------------------------*/
extern int __STACK_TOP;
/* Function prototypes -----------------------------------------------------*/
void Reset_Handler (void); /* Reset Handler */
void Default_Handler(void); /* Default empty handler */
/*--------------------------------------------------------------------------*/
/* Cortex-M Processor fault exceptions... */
void NMI_Handler (void);
void HardFault_Handler (void);
void MemManage_Handler (void);
void BusFault_Handler (void);
void UsageFault_Handler (void);
/* Cortex-M Processor non-fault exceptions... */
void SVC_Handler (void);
void DebugMon_Handler (void);
void PendSV_Handler (void);
void SysTick_Handler (void);
/* external interrupts... */
void GPIOPortA_IRQHandler (void);
void GPIOPortB_IRQHandler (void);
void GPIOPortC_IRQHandler (void);
void GPIOPortD_IRQHandler (void);
void GPIOPortE_IRQHandler (void);
void UART0_IRQHandler (void);
void UART1_IRQHandler (void);
void SSI0_IRQHandler (void);
void I2C0_IRQHandler (void);
void PWMFault_IRQHandler (void);
void PWMGen0_IRQHandler (void);
void PWMGen1_IRQHandler (void);
void PWMGen2_IRQHandler (void);
void QEI0_IRQHandler (void);
void ADCSeq0_IRQHandler (void);
void ADCSeq1_IRQHandler (void);
void ADCSeq2_IRQHandler (void);
void ADCSeq3_IRQHandler (void);
void Watchdog_IRQHandler (void);
void Timer0A_IRQHandler (void);
void Timer0B_IRQHandler (void);
void Timer1A_IRQHandler (void);
void Timer1B_IRQHandler (void);
void Timer2A_IRQHandler (void);
void Timer2B_IRQHandler (void);
void Comp0_IRQHandler (void);
void Comp1_IRQHandler (void);
void Comp2_IRQHandler (void);
void SysCtrl_IRQHandler (void);
void FlashCtrl_IRQHandler (void);
void GPIOPortF_IRQHandler (void);
void GPIOPortG_IRQHandler (void);
void GPIOPortH_IRQHandler (void);
void UART2_IRQHandler (void);
void SSI1_IRQHandler (void);
void Timer3A_IRQHandler (void);
void Timer3B_IRQHandler (void);
void I2C1_IRQHandler (void);
void QEI1_IRQHandler (void);
void CAN0_IRQHandler (void);
void CAN1_IRQHandler (void);
void CAN2_IRQHandler (void);
void Hibernate_IRQHandler (void);
void USB0_IRQHandler (void);
void PWMGen3_IRQHandler (void);
void uDMAST_IRQHandler (void);
void uDMAError_IRQHandler (void);
void ADC1Seq0_IRQHandler (void);
void ADC1Seq1_IRQHandler (void);
void ADC1Seq2_IRQHandler (void);
void ADC1Seq3_IRQHandler (void);
void GPIOPortJ_IRQHandler (void);
void GPIOPortK_IRQHandler (void);
void GPIOPortL_IRQHandler (void);
void SSI2_IRQHandler (void);
void SSI3_IRQHandler (void);
void UART3_IRQHandler (void);
void UART4_IRQHandler (void);
void UART5_IRQHandler (void);
void UART6_IRQHandler (void);
void UART7_IRQHandler (void);
void I2C2_IRQHandler (void);
void I2C3_IRQHandler (void);
void Timer4A_IRQHandler (void);
void Timer4B_IRQHandler (void);
void Timer5A_IRQHandler (void);
void Timer5B_IRQHandler (void);
void WideTimer0A_IRQHandler(void);
void WideTimer0B_IRQHandler(void);
void WideTimer1A_IRQHandler(void);
void WideTimer1B_IRQHandler(void);
void WideTimer2A_IRQHandler(void);
void WideTimer2B_IRQHandler(void);
void WideTimer3A_IRQHandler(void);
void WideTimer3B_IRQHandler(void);
void WideTimer4A_IRQHandler(void);
void WideTimer4B_IRQHandler(void);
void WideTimer5A_IRQHandler(void);
void WideTimer5B_IRQHandler(void);
void FPU_IRQHandler (void);
void I2C4_IRQHandler (void);
void I2C5_IRQHandler (void);
void GPIOPortM_IRQHandler (void);
void GPIOPortN_IRQHandler (void);
void QEI2_IRQHandler (void);
void GPIOPortP0_IRQHandler (void);
void GPIOPortP1_IRQHandler (void);
void GPIOPortP2_IRQHandler (void);
void GPIOPortP3_IRQHandler (void);
void GPIOPortP4_IRQHandler (void);
void GPIOPortP5_IRQHandler (void);
void GPIOPortP6_IRQHandler (void);
void GPIOPortP7_IRQHandler (void);
void GPIOPortQ0_IRQHandler (void);
void GPIOPortQ1_IRQHandler (void);
void GPIOPortQ2_IRQHandler (void);
void GPIOPortQ3_IRQHandler (void);
void GPIOPortQ4_IRQHandler (void);
void GPIOPortQ5_IRQHandler (void);
void GPIOPortQ6_IRQHandler (void);
void GPIOPortQ7_IRQHandler (void);
void GPIOPortR_IRQHandler (void);
void GPIOPortS_IRQHandler (void);
void PWM1Gen0_IRQHandler (void);
void PWM1Gen1_IRQHandler (void);
void PWM1Gen2_IRQHandler (void);
void PWM1Gen3_IRQHandler (void);
void PWM1Fault_IRQHandler (void);
//*****************************************************************************
//
// The vector table. Note that the proper constructs must be placed on this to
// ensure that it ends up at physical address 0x0000.0000 or at the start of
// the program if located at a start address other than 0.
//
// !!!!!! NOTE !!!!!!
// You must MANUALLY remove the (int)&Default_Handler from the interrupts
// that you actually wish to handle in your application!
//*****************************************************************************
#pragma DATA_SECTION(g_pfnVectors, ".intvecs")
int const g_pfnVectors[] = {
(int)&__STACK_TOP, /* The initial stack pointer */
(int)&Reset_Handler, /* Reset Handler */
(int)&NMI_Handler, /* NMI Handler */
(int)&HardFault_Handler, /* Hard Fault Handler */
(int)&MemManage_Handler, /* The MPU fault handler */
(int)&BusFault_Handler, /* The bus fault handler */
(int)&UsageFault_Handler, /* The usage fault handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
(int)&SVC_Handler, /* SVCall handler */
(int)&DebugMon_Handler, /* Debug monitor handler */
0, /* Reserved */
(int)&PendSV_Handler, /* The PendSV handler */
(int)&SysTick_Handler, /* The SysTick handler */
/* IRQ handlers... */
(int)&Default_Handler, //(int)&GPIOPortA_IRQHandler, /* GPIO Port A */
(int)&Default_Handler, //(int)&GPIOPortB_IRQHandler, /* GPIO Port B */
(int)&Default_Handler, //(int)&GPIOPortC_IRQHandler, /* GPIO Port C */
(int)&Default_Handler, //(int)&GPIOPortD_IRQHandler, /* GPIO Port D */
(int)&Default_Handler, //(int)&GPIOPortE_IRQHandler, /* GPIO Port E */
(int)&UART0_IRQHandler, /* UART0 Rx and Tx */
(int)&Default_Handler, //(int)&UART1_IRQHandler, /* UART1 Rx and Tx */
(int)&Default_Handler, //(int)&SSI0_IRQHandler, /* SSI0 Rx and Tx */
(int)&Default_Handler, //(int)&I2C0_IRQHandler, /* I2C0 Master and Slave */
(int)&Default_Handler, //(int)&PWMFault_IRQHandler, /* PWM Fault */
(int)&Default_Handler, //(int)&PWMGen0_IRQHandler, /* PWM Generator 0 */
(int)&Default_Handler, //(int)&PWMGen1_IRQHandler, /* PWM Generator 1 */
(int)&Default_Handler, //(int)&PWMGen2_IRQHandler, /* PWM Generator 2 */
(int)&Default_Handler, //(int)&QEI0_IRQHandler, /* Quadrature Encoder 0 */
(int)&Default_Handler, //(int)&ADCSeq0_IRQHandler, /* ADC Sequence 0 */
(int)&Default_Handler, //(int)&ADCSeq1_IRQHandler, /* ADC Sequence 1 */
(int)&Default_Handler, //(int)&ADCSeq2_IRQHandler, /* ADC Sequence 2 */
(int)&Default_Handler, //(int)&ADCSeq3_IRQHandler, /* ADC Sequence 3 */
(int)&Default_Handler, //(int)&Watchdog_IRQHandler, /* Watchdog timer */
(int)&Default_Handler, //(int)&Timer0A_IRQHandler, /* Timer 0 subtimer A */
(int)&Default_Handler, //(int)&Timer0B_IRQHandler, /* Timer 0 subtimer B */
(int)&Default_Handler, //(int)&Timer1A_IRQHandler, /* Timer 1 subtimer A */
(int)&Default_Handler, //(int)&Timer1B_IRQHandler, /* Timer 1 subtimer B */
(int)&Default_Handler, //(int)&Timer2A_IRQHandler, /* Timer 2 subtimer A */
(int)&Default_Handler, //(int)&Timer2B_IRQHandler, /* Timer 2 subtimer B */
(int)&Default_Handler, //(int)&Comp0_IRQHandler, /* Analog Comparator 0 */
(int)&Default_Handler, //(int)&Comp1_IRQHandler, /* Analog Comparator 1 */
(int)&Default_Handler, //(int)&Comp2_IRQHandler, /* Analog Comparator 2 */
(int)&Default_Handler, //(int)&SysCtrl_IRQHandler, /* System Control (PLL, OSC, BO) */
(int)&Default_Handler, //(int)&FlashCtrl_IRQHandler, /* FLASH Control */
(int)&Default_Handler, //(int)&GPIOPortF_IRQHandler, /* GPIO Port F */
(int)&Default_Handler, //(int)&GPIOPortG_IRQHandler, /* GPIO Port G */
(int)&Default_Handler, //(int)&GPIOPortH_IRQHandler, /* GPIO Port H */
(int)&Default_Handler, //(int)&UART2_IRQHandler, /* UART2 Rx and Tx */
(int)&Default_Handler, //(int)&SSI1_IRQHandler, /* SSI1 Rx and Tx */
(int)&Default_Handler, //(int)&Timer3A_IRQHandler, /* Timer 3 subtimer A */
(int)&Default_Handler, //(int)&Timer3B_IRQHandler, /* Timer 3 subtimer B */
(int)&Default_Handler, //(int)&I2C1_IRQHandler, /* I2C1 Master and Slave */
(int)&Default_Handler, //(int)&QEI1_IRQHandler, /* Quadrature Encoder 1 */
(int)&Default_Handler, //(int)&CAN0_IRQHandler, /* CAN0 */
(int)&Default_Handler, //(int)&CAN1_IRQHandler, /* CAN1 */
(int)&Default_Handler, //(int)&CAN2_IRQHandler, /* CAN2 */
(int)&Default_Handler, //0, /* Reserved */
(int)&Default_Handler, //(int)&Hibernate_IRQHandler, /* Hibernate */
(int)&Default_Handler, //(int)&USB0_IRQHandler, /* USB0 */
(int)&Default_Handler, //(int)&PWMGen3_IRQHandler, /* PWM Generator 3 */
(int)&Default_Handler, //(int)&uDMAST_IRQHandler, /* uDMA Software Transfer */
(int)&Default_Handler, //(int)&uDMAError_IRQHandler, /* uDMA Error */
(int)&Default_Handler, //(int)&ADC1Seq0_IRQHandler, /* ADC1 Sequence 0 */
(int)&Default_Handler, //(int)&ADC1Seq1_IRQHandler, /* ADC1 Sequence 1 */
(int)&Default_Handler, //(int)&ADC1Seq2_IRQHandler, /* ADC1 Sequence 2 */
(int)&Default_Handler, //(int)&ADC1Seq3_IRQHandler, /* ADC1 Sequence 3 */
0, /* Reserved */
0, /* Reserved */
(int)&Default_Handler, //(int)&GPIOPortJ_IRQHandler, /* GPIO Port J */
(int)&Default_Handler, //(int)&GPIOPortK_IRQHandler, /* GPIO Port K */
(int)&Default_Handler, //(int)&GPIOPortL_IRQHandler, /* GPIO Port L */
(int)&Default_Handler, //(int)&SSI2_IRQHandler, /* SSI2 Rx and Tx */
(int)&Default_Handler, //(int)&SSI3_IRQHandler, /* SSI3 Rx and Tx */
(int)&Default_Handler, //(int)&UART3_IRQHandler, /* UART3 Rx and Tx */
(int)&Default_Handler, //(int)&UART4_IRQHandler, /* UART4 Rx and Tx */
(int)&Default_Handler, //(int)&UART5_IRQHandler, /* UART5 Rx and Tx */
(int)&Default_Handler, //(int)&UART6_IRQHandler, /* UART6 Rx and Tx */
(int)&Default_Handler, //(int)&UART7_IRQHandler, /* UART7 Rx and Tx */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
(int)&Default_Handler, //(int)&I2C2_IRQHandler, /* I2C2 Master and Slave */
(int)&Default_Handler, //(int)&I2C3_IRQHandler, /* I2C3 Master and Slave */
(int)&Default_Handler, //(int)&Timer4A_IRQHandler, /* Timer 4 subtimer A */
(int)&Default_Handler, //(int)&Timer4B_IRQHandler, /* Timer 4 subtimer B */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
(int)&Default_Handler, //(int)&Timer5A_IRQHandler, /* Timer 5 subtimer A */
(int)&Default_Handler, //(int)&Timer5B_IRQHandler, /* Timer 5 subtimer B */
(int)&Default_Handler, //(int)&WideTimer0A_IRQHandler, /* Wide Timer 0 subtimer A */
(int)&Default_Handler, //(int)&WideTimer0B_IRQHandler, /* Wide Timer 0 subtimer B */
(int)&Default_Handler, //(int)&WideTimer1A_IRQHandler, /* Wide Timer 1 subtimer A */
(int)&Default_Handler, //(int)&WideTimer1B_IRQHandler, /* Wide Timer 1 subtimer B */
(int)&Default_Handler, //(int)&WideTimer2A_IRQHandler, /* Wide Timer 2 subtimer A */
(int)&Default_Handler, //(int)&WideTimer2B_IRQHandler, /* Wide Timer 2 subtimer B */
(int)&Default_Handler, //(int)&WideTimer3A_IRQHandler, /* Wide Timer 3 subtimer A */
(int)&Default_Handler, //(int)&WideTimer3B_IRQHandler, /* Wide Timer 3 subtimer B */
(int)&Default_Handler, //(int)&WideTimer4A_IRQHandler, /* Wide Timer 4 subtimer A */
(int)&Default_Handler, //(int)&WideTimer4B_IRQHandler, /* Wide Timer 4 subtimer B */
(int)&Default_Handler, //(int)&WideTimer5A_IRQHandler, /* Wide Timer 5 subtimer A */
(int)&Default_Handler, //(int)&WideTimer5B_IRQHandler, /* Wide Timer 5 subtimer B */
(int)&Default_Handler, //(int)&FPU_IRQHandler, /* FPU */
0, /* Reserved */
0, /* Reserved */
(int)&Default_Handler, //(int)&I2C4_IRQHandler, /* I2C4 Master and Slave */
(int)&Default_Handler, //(int)&I2C5_IRQHandler, /* I2C5 Master and Slave */
(int)&Default_Handler, //(int)&GPIOPortM_IRQHandler, /* GPIO Port M */
(int)&Default_Handler, //(int)&GPIOPortN_IRQHandler, /* GPIO Port N */
(int)&Default_Handler, //(int)&QEI2_IRQHandler, /* Quadrature Encoder 2 */
0, /* Reserved */
0, /* Reserved */
(int)&Default_Handler, //(int)&GPIOPortP0_IRQHandler, /* GPIO Port P (Summary or P0) */
(int)&Default_Handler, //(int)&GPIOPortP1_IRQHandler, /* GPIO Port P1 */
(int)&Default_Handler, //(int)&GPIOPortP2_IRQHandler, /* GPIO Port P2 */
(int)&Default_Handler, //(int)&GPIOPortP3_IRQHandler, /* GPIO Port P3 */
(int)&Default_Handler, //(int)&GPIOPortP4_IRQHandler, /* GPIO Port P4 */
(int)&Default_Handler, //(int)&GPIOPortP5_IRQHandler, /* GPIO Port P5 */
(int)&Default_Handler, //(int)&GPIOPortP6_IRQHandler, /* GPIO Port P6 */
(int)&Default_Handler, //(int)&GPIOPortP7_IRQHandler, /* GPIO Port P7 */
(int)&Default_Handler, //(int)&GPIOPortQ0_IRQHandler, /* GPIO Port Q (Summary or Q0) */
(int)&Default_Handler, //(int)&GPIOPortQ1_IRQHandler, /* GPIO Port Q1 */
(int)&Default_Handler, //(int)&GPIOPortQ2_IRQHandler, /* GPIO Port Q2 */
(int)&Default_Handler, //(int)&GPIOPortQ3_IRQHandler, /* GPIO Port Q3 */
(int)&Default_Handler, //(int)&GPIOPortQ4_IRQHandler, /* GPIO Port Q4 */
(int)&Default_Handler, //(int)&GPIOPortQ5_IRQHandler, /* GPIO Port Q5 */
(int)&Default_Handler, //(int)&GPIOPortQ6_IRQHandler, /* GPIO Port Q6 */
(int)&Default_Handler, //(int)&GPIOPortQ7_IRQHandler, /* GPIO Port Q7 */
(int)&Default_Handler, //(int)&GPIOPortR_IRQHandler, /* GPIO Port R */
(int)&Default_Handler, //(int)&GPIOPortS_IRQHandler, /* GPIO Port S */
(int)&Default_Handler, //(int)&PWM1Gen0_IRQHandler, /* PWM 1 Generator 0 */
(int)&Default_Handler, //(int)&PWM1Gen1_IRQHandler, /* PWM 1 Generator 1 */
(int)&Default_Handler, //(int)&PWM1Gen2_IRQHandler, /* PWM 1 Generator 2 */
(int)&Default_Handler, //(int)&PWM1Gen3_IRQHandler, /* PWM 1 Generator 3 */
(int)&Default_Handler, //(int)&PWM1Fault_IRQHandler, /* PWM 1 Fault */
};
//*****************************************************************************
//
// This is the code that gets called when the processor first starts execution
// following a reset event. Only the absolutely necessary set is performed,
// after which the application supplied entry() routine is called. Any fancy
// actions (such as making decisions based on the reset cause register, and
// resetting the bits in that register) are left solely in the hands of the
// application.
//
//*****************************************************************************
void Reset_Handler(void) {
// First, call the CMSIS SystemInit() to set up the CPU clock.
// Next, jump to the CCS C initialization routine. This will enable the
// floating-point unit as well, so that does not need to be done here.
//
__asm volatile(
" .global _c_int00\n\r"
" .global SystemInit\n\r"
" bl.w SystemInit\n\r"
" b.w _c_int00\n\r");
}
/* fault exception handlers ------------------------------------------------*/
void Default_Handler(void) {
__asm volatile (
" .global assert_failed\n\r"
" mov r0,#0\n\r"
" mov r1,#0\n\r"
" b.w assert_failed\n\r"
);
}
/*..........................................................................*/
void NMI_Handler(void) {
__asm(
" .global assert_failed\n\r"
" mov r0,#0\n\r"
" mov r1,#1\n\r"
" b.w assert_failed\n\r"
);
}
/*..........................................................................*/
void MemManage_Handler(void) {
__asm(
" .global assert_failed\n\r"
" mov r0,#0\n\r"
" mov r1,#2\n\r"
" b.w assert_failed\n\r"
);
}
/*..........................................................................*/
void HardFault_Handler(void) {
__asm volatile (
" .global assert_failed\n\r"
" mov r0,#0\n\r"
" mov r1,#3\n\r"
" b.w assert_failed\n\r"
);
}
/*..........................................................................*/
void BusFault_Handler(void) {
__asm volatile (
" .global assert_failed\n\r"
" mov r0,#0\n\r"
" mov r1,#4\n\r"
" b.w assert_failed\n\r"
);
}
/*..........................................................................*/
void UsageFault_Handler(void) {
__asm volatile (
" .global assert_failed\n\r"
" mov r0,#0\n\r"
" mov r1,#5\n\r"
" b.w assert_failed\n\r"
);
}
/*..........................................................................*/
void DebugMon_Handler(void) {
__asm volatile (
" .global assert_failed\n\r"
" mov r0,#0\n\r"
" mov r1,#6\n\r"
" b.w assert_failed\n\r"
);
}
/*..........................................................................*/
void _init(void) { /* dummy */
}
/*..........................................................................*/
void _fini(void) { /* dummy */
}

13
examples/arm-cm/dpp_ek-tm4c123gxl/qk/ti/targetConfigs/Tiva TM4C123GH6PM.ccxml Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<configurations XML_version="1.2" id="configurations_0">
<configuration XML_version="1.2" id="configuration_0">
<instance XML_version="1.2" desc="Stellaris In-Circuit Debug Interface" href="connections/Stellaris_ICDI_Connection.xml" id="Stellaris In-Circuit Debug Interface" xml="Stellaris_ICDI_Connection.xml" xmlpath="connections"/>
<connection XML_version="1.2" id="Stellaris In-Circuit Debug Interface">
<instance XML_version="1.2" href="drivers/stellaris_cs_dap.xml" id="drivers" xml="stellaris_cs_dap.xml" xmlpath="drivers"/>
<instance XML_version="1.2" href="drivers/stellaris_cortex_m4.xml" id="drivers" xml="stellaris_cortex_m4.xml" xmlpath="drivers"/>
<platform XML_version="1.2" id="platform_0">
<instance XML_version="1.2" desc="Tiva TM4C123GH6PM" href="devices/tm4c123gh6pm.xml" id="Tiva TM4C123GH6PM" xml="tm4c123gh6pm.xml" xmlpath="devices"/>
</platform>
</connection>
</configuration>
</configurations>

9
examples/arm-cm/dpp_ek-tm4c123gxl/qk/ti/targetConfigs/readme.txt Normal file
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@ -0,0 +1,9 @@
The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based
on the device and connection settings specified in your project on the Properties > General page.
Please note that in automatic target-configuration management, changes to the project's device and/or
connection settings will either modify an existing or generate a new target-configuration file. Thus,
if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively,
you may create your own target-configuration file for this project and manage it manually. You can
always switch back to automatic target-configuration management by checking the "Manage the project's
target-configuration automatically" checkbox on the project's Properties > General page.

45
examples/arm-cm/dpp_ek-tm4c123gxl/qk/ti/tm4c123gh6pm.cmd Normal file
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@ -0,0 +1,45 @@
/******************************************************************************
*
* Default Linker Command file for the Texas Instruments TM4C123GH6PM
*
* This is derived from revision 14351 of the TivaWare Library.
*
*****************************************************************************/
--retain=g_pfnVectors
MEMORY
{
FLASH (RX) : origin = 0x00000000, length = 0x00040000
SRAM (RWX) : origin = 0x20000000, length = 0x00008000
}
/* The following command line options are set as part of the CCS project. */
/* If you are building using the command line, or for some reason want to */
/* define them here, you can uncomment and modify these lines as needed. */
/* If you are using CCS for building, it is probably better to make any such */
/* modifications in your CCS project and leave this file alone. */
/* */
/* --heap_size=0 */
/* --stack_size=256 */
/* --library=rtsv7M4_T_le_eabi.lib */
/* Section allocation in memory */
SECTIONS
{
.intvecs: > 0x00000000
.text : > FLASH
.const : > FLASH
.cinit : > FLASH
.pinit : > FLASH
.init_array : > FLASH
.vtable : > 0x20000000
.data : > SRAM
.bss : > SRAM
.sysmem : > SRAM
.stack : > SRAM
}
__STACK_TOP = __stack + 512;

15
examples/arm-cm/dpp_ek-tm4c123gxl/qv/ti/.ccsproject Normal file
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@ -0,0 +1,15 @@
<?xml version="1.0" encoding="UTF-8" ?>
<?ccsproject version="1.0"?>
<projectOptions>
<deviceVariant value="Cortex M.TM4C123GH6PM"/>
<deviceFamily value="TMS470"/>
<deviceEndianness value="little"/>
<codegenToolVersion value="5.2.5"/>
<isElfFormat value="true"/>
<connection value="common/targetdb/connections/Stellaris_ICDI_Connection.xml"/>
<linkerCommandFile value="tm4c123gh6pm.cmd"/>
<rts value="libc.a"/>
<createSlaveProjects value=""/>
<templateProperties value="id=com.ti.common.project.core.emptyProjectTemplate,"/>
<isTargetManual value="false"/>
</projectOptions>

296
examples/arm-cm/dpp_ek-tm4c123gxl/qv/ti/.cproject Normal file
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17
examples/arm-cm/dpp_ek-tm4c123gxl/qv/ti/.launches/dpp-qv.launch Normal file
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@ -0,0 +1,17 @@
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79
examples/arm-cm/dpp_ek-tm4c123gxl/qv/ti/.project Normal file
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@ -0,0 +1,79 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>dpp-qv</name>
<comment></comment>
<projects>
</projects>
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<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
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</arguments>
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<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
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3
examples/arm-cm/dpp_ek-tm4c123gxl/qv/ti/.settings/org.eclipse.cdt.codan.core.prefs Normal file
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eclipse.preferences.version=1
inEditor=false
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5
examples/arm-cm/dpp_ek-tm4c123gxl/qv/ti/.settings/org.eclipse.cdt.core.prefs Normal file
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eclipse.preferences.version=1
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environment/project/com.ti.ccstudio.buildDefinitions.TMS470.Debug.1412738644/appendContributed=true

2
examples/arm-cm/dpp_ek-tm4c123gxl/qv/ti/.settings/org.eclipse.cdt.debug.core.prefs Normal file
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40
examples/arm-cm/dpp_ek-tm4c123gxl/qv/ti/.settings/org.eclipse.core.resources.prefs Normal file
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434
examples/arm-cm/dpp_ek-tm4c123gxl/qv/ti/startup_TM4C123GH6PM.c Normal file
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@ -0,0 +1,434 @@
/* File: startup_TM4C123GH6PM.c
* Purpose: startup file for TM4C123GH6PM Cortex-M4 device.
* Should be used with TI CCS-ARM Compiler
* Version: CMSIS 4.3.0
* Date: 5 October 2015
*
* Created from the CMSIS template for the specified device
* Quantum Leaps, www.state-machine.com
*
* NOTE:
* The function assert_failed defined at the end of this file defines
* the error/assertion handling policy for the application and might
* need to be customized for each project. This function is defined in
* assembly to re-set the stack pointer, in case it is corrupted by the
* time assert_failed is called.
*/
//****************************************************************************
//
// Startup code for use with TI's Code Composer Studio.
//
// Copyright (c) 2011-2014 Texas Instruments Inc. All rights reserved.
// Software License Agreement
//
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
//****************************************************************************
/* top of stack defined in the linker script -------------------------------*/
extern int __STACK_TOP;
/* Function prototypes -----------------------------------------------------*/
void Reset_Handler (void); /* Reset Handler */
void Default_Handler(void); /* Default empty handler */
/*--------------------------------------------------------------------------*/
/* Cortex-M Processor fault exceptions... */
void NMI_Handler (void);
void HardFault_Handler (void);
void MemManage_Handler (void);
void BusFault_Handler (void);
void UsageFault_Handler (void);
/* Cortex-M Processor non-fault exceptions... */
void SVC_Handler (void);
void DebugMon_Handler (void);
void PendSV_Handler (void);
void SysTick_Handler (void);
/* external interrupts... */
void GPIOPortA_IRQHandler (void);
void GPIOPortB_IRQHandler (void);
void GPIOPortC_IRQHandler (void);
void GPIOPortD_IRQHandler (void);
void GPIOPortE_IRQHandler (void);
void UART0_IRQHandler (void);
void UART1_IRQHandler (void);
void SSI0_IRQHandler (void);
void I2C0_IRQHandler (void);
void PWMFault_IRQHandler (void);
void PWMGen0_IRQHandler (void);
void PWMGen1_IRQHandler (void);
void PWMGen2_IRQHandler (void);
void QEI0_IRQHandler (void);
void ADCSeq0_IRQHandler (void);
void ADCSeq1_IRQHandler (void);
void ADCSeq2_IRQHandler (void);
void ADCSeq3_IRQHandler (void);
void Watchdog_IRQHandler (void);
void Timer0A_IRQHandler (void);
void Timer0B_IRQHandler (void);
void Timer1A_IRQHandler (void);
void Timer1B_IRQHandler (void);
void Timer2A_IRQHandler (void);
void Timer2B_IRQHandler (void);
void Comp0_IRQHandler (void);
void Comp1_IRQHandler (void);
void Comp2_IRQHandler (void);
void SysCtrl_IRQHandler (void);
void FlashCtrl_IRQHandler (void);
void GPIOPortF_IRQHandler (void);
void GPIOPortG_IRQHandler (void);
void GPIOPortH_IRQHandler (void);
void UART2_IRQHandler (void);
void SSI1_IRQHandler (void);
void Timer3A_IRQHandler (void);
void Timer3B_IRQHandler (void);
void I2C1_IRQHandler (void);
void QEI1_IRQHandler (void);
void CAN0_IRQHandler (void);
void CAN1_IRQHandler (void);
void CAN2_IRQHandler (void);
void Hibernate_IRQHandler (void);
void USB0_IRQHandler (void);
void PWMGen3_IRQHandler (void);
void uDMAST_IRQHandler (void);
void uDMAError_IRQHandler (void);
void ADC1Seq0_IRQHandler (void);
void ADC1Seq1_IRQHandler (void);
void ADC1Seq2_IRQHandler (void);
void ADC1Seq3_IRQHandler (void);
void GPIOPortJ_IRQHandler (void);
void GPIOPortK_IRQHandler (void);
void GPIOPortL_IRQHandler (void);
void SSI2_IRQHandler (void);
void SSI3_IRQHandler (void);
void UART3_IRQHandler (void);
void UART4_IRQHandler (void);
void UART5_IRQHandler (void);
void UART6_IRQHandler (void);
void UART7_IRQHandler (void);
void I2C2_IRQHandler (void);
void I2C3_IRQHandler (void);
void Timer4A_IRQHandler (void);
void Timer4B_IRQHandler (void);
void Timer5A_IRQHandler (void);
void Timer5B_IRQHandler (void);
void WideTimer0A_IRQHandler(void);
void WideTimer0B_IRQHandler(void);
void WideTimer1A_IRQHandler(void);
void WideTimer1B_IRQHandler(void);
void WideTimer2A_IRQHandler(void);
void WideTimer2B_IRQHandler(void);
void WideTimer3A_IRQHandler(void);
void WideTimer3B_IRQHandler(void);
void WideTimer4A_IRQHandler(void);
void WideTimer4B_IRQHandler(void);
void WideTimer5A_IRQHandler(void);
void WideTimer5B_IRQHandler(void);
void FPU_IRQHandler (void);
void I2C4_IRQHandler (void);
void I2C5_IRQHandler (void);
void GPIOPortM_IRQHandler (void);
void GPIOPortN_IRQHandler (void);
void QEI2_IRQHandler (void);
void GPIOPortP0_IRQHandler (void);
void GPIOPortP1_IRQHandler (void);
void GPIOPortP2_IRQHandler (void);
void GPIOPortP3_IRQHandler (void);
void GPIOPortP4_IRQHandler (void);
void GPIOPortP5_IRQHandler (void);
void GPIOPortP6_IRQHandler (void);
void GPIOPortP7_IRQHandler (void);
void GPIOPortQ0_IRQHandler (void);
void GPIOPortQ1_IRQHandler (void);
void GPIOPortQ2_IRQHandler (void);
void GPIOPortQ3_IRQHandler (void);
void GPIOPortQ4_IRQHandler (void);
void GPIOPortQ5_IRQHandler (void);
void GPIOPortQ6_IRQHandler (void);
void GPIOPortQ7_IRQHandler (void);
void GPIOPortR_IRQHandler (void);
void GPIOPortS_IRQHandler (void);
void PWM1Gen0_IRQHandler (void);
void PWM1Gen1_IRQHandler (void);
void PWM1Gen2_IRQHandler (void);
void PWM1Gen3_IRQHandler (void);
void PWM1Fault_IRQHandler (void);
//*****************************************************************************
//
// The vector table. Note that the proper constructs must be placed on this to
// ensure that it ends up at physical address 0x0000.0000 or at the start of
// the program if located at a start address other than 0.
//
// !!!!!! NOTE !!!!!!
// You must MANUALLY remove the (int)&Default_Handler from the interrupts
// that you actually wish to handle in your application!
//*****************************************************************************
#pragma DATA_SECTION(g_pfnVectors, ".intvecs")
int const g_pfnVectors[] = {
(int)&__STACK_TOP, /* The initial stack pointer */
(int)&Reset_Handler, /* Reset Handler */
(int)&NMI_Handler, /* NMI Handler */
(int)&HardFault_Handler, /* Hard Fault Handler */
(int)&MemManage_Handler, /* The MPU fault handler */
(int)&BusFault_Handler, /* The bus fault handler */
(int)&UsageFault_Handler, /* The usage fault handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
(int)&Default_Handler, //(int)&SVC_Handler, /* SVCall handler */
(int)&DebugMon_Handler, /* Debug monitor handler */
0, /* Reserved */
(int)&Default_Handler, //(int)&PendSV_Handler, /* The PendSV handler */
(int)&SysTick_Handler, /* The SysTick handler */
/* IRQ handlers... */
(int)&Default_Handler, //(int)&GPIOPortA_IRQHandler, /* GPIO Port A */
(int)&Default_Handler, //(int)&GPIOPortB_IRQHandler, /* GPIO Port B */
(int)&Default_Handler, //(int)&GPIOPortC_IRQHandler, /* GPIO Port C */
(int)&Default_Handler, //(int)&GPIOPortD_IRQHandler, /* GPIO Port D */
(int)&Default_Handler, //(int)&GPIOPortE_IRQHandler, /* GPIO Port E */
(int)&UART0_IRQHandler, /* UART0 Rx and Tx */
(int)&Default_Handler, //(int)&UART1_IRQHandler, /* UART1 Rx and Tx */
(int)&Default_Handler, //(int)&SSI0_IRQHandler, /* SSI0 Rx and Tx */
(int)&Default_Handler, //(int)&I2C0_IRQHandler, /* I2C0 Master and Slave */
(int)&Default_Handler, //(int)&PWMFault_IRQHandler, /* PWM Fault */
(int)&Default_Handler, //(int)&PWMGen0_IRQHandler, /* PWM Generator 0 */
(int)&Default_Handler, //(int)&PWMGen1_IRQHandler, /* PWM Generator 1 */
(int)&Default_Handler, //(int)&PWMGen2_IRQHandler, /* PWM Generator 2 */
(int)&Default_Handler, //(int)&QEI0_IRQHandler, /* Quadrature Encoder 0 */
(int)&Default_Handler, //(int)&ADCSeq0_IRQHandler, /* ADC Sequence 0 */
(int)&Default_Handler, //(int)&ADCSeq1_IRQHandler, /* ADC Sequence 1 */
(int)&Default_Handler, //(int)&ADCSeq2_IRQHandler, /* ADC Sequence 2 */
(int)&Default_Handler, //(int)&ADCSeq3_IRQHandler, /* ADC Sequence 3 */
(int)&Default_Handler, //(int)&Watchdog_IRQHandler, /* Watchdog timer */
(int)&Default_Handler, //(int)&Timer0A_IRQHandler, /* Timer 0 subtimer A */
(int)&Default_Handler, //(int)&Timer0B_IRQHandler, /* Timer 0 subtimer B */
(int)&Default_Handler, //(int)&Timer1A_IRQHandler, /* Timer 1 subtimer A */
(int)&Default_Handler, //(int)&Timer1B_IRQHandler, /* Timer 1 subtimer B */
(int)&Default_Handler, //(int)&Timer2A_IRQHandler, /* Timer 2 subtimer A */
(int)&Default_Handler, //(int)&Timer2B_IRQHandler, /* Timer 2 subtimer B */
(int)&Default_Handler, //(int)&Comp0_IRQHandler, /* Analog Comparator 0 */
(int)&Default_Handler, //(int)&Comp1_IRQHandler, /* Analog Comparator 1 */
(int)&Default_Handler, //(int)&Comp2_IRQHandler, /* Analog Comparator 2 */
(int)&Default_Handler, //(int)&SysCtrl_IRQHandler, /* System Control (PLL, OSC, BO) */
(int)&Default_Handler, //(int)&FlashCtrl_IRQHandler, /* FLASH Control */
(int)&Default_Handler, //(int)&GPIOPortF_IRQHandler, /* GPIO Port F */
(int)&Default_Handler, //(int)&GPIOPortG_IRQHandler, /* GPIO Port G */
(int)&Default_Handler, //(int)&GPIOPortH_IRQHandler, /* GPIO Port H */
(int)&Default_Handler, //(int)&UART2_IRQHandler, /* UART2 Rx and Tx */
(int)&Default_Handler, //(int)&SSI1_IRQHandler, /* SSI1 Rx and Tx */
(int)&Default_Handler, //(int)&Timer3A_IRQHandler, /* Timer 3 subtimer A */
(int)&Default_Handler, //(int)&Timer3B_IRQHandler, /* Timer 3 subtimer B */
(int)&Default_Handler, //(int)&I2C1_IRQHandler, /* I2C1 Master and Slave */
(int)&Default_Handler, //(int)&QEI1_IRQHandler, /* Quadrature Encoder 1 */
(int)&Default_Handler, //(int)&CAN0_IRQHandler, /* CAN0 */
(int)&Default_Handler, //(int)&CAN1_IRQHandler, /* CAN1 */
(int)&Default_Handler, //(int)&CAN2_IRQHandler, /* CAN2 */
(int)&Default_Handler, //0, /* Reserved */
(int)&Default_Handler, //(int)&Hibernate_IRQHandler, /* Hibernate */
(int)&Default_Handler, //(int)&USB0_IRQHandler, /* USB0 */
(int)&Default_Handler, //(int)&PWMGen3_IRQHandler, /* PWM Generator 3 */
(int)&Default_Handler, //(int)&uDMAST_IRQHandler, /* uDMA Software Transfer */
(int)&Default_Handler, //(int)&uDMAError_IRQHandler, /* uDMA Error */
(int)&Default_Handler, //(int)&ADC1Seq0_IRQHandler, /* ADC1 Sequence 0 */
(int)&Default_Handler, //(int)&ADC1Seq1_IRQHandler, /* ADC1 Sequence 1 */
(int)&Default_Handler, //(int)&ADC1Seq2_IRQHandler, /* ADC1 Sequence 2 */
(int)&Default_Handler, //(int)&ADC1Seq3_IRQHandler, /* ADC1 Sequence 3 */
0, /* Reserved */
0, /* Reserved */
(int)&Default_Handler, //(int)&GPIOPortJ_IRQHandler, /* GPIO Port J */
(int)&Default_Handler, //(int)&GPIOPortK_IRQHandler, /* GPIO Port K */
(int)&Default_Handler, //(int)&GPIOPortL_IRQHandler, /* GPIO Port L */
(int)&Default_Handler, //(int)&SSI2_IRQHandler, /* SSI2 Rx and Tx */
(int)&Default_Handler, //(int)&SSI3_IRQHandler, /* SSI3 Rx and Tx */
(int)&Default_Handler, //(int)&UART3_IRQHandler, /* UART3 Rx and Tx */
(int)&Default_Handler, //(int)&UART4_IRQHandler, /* UART4 Rx and Tx */
(int)&Default_Handler, //(int)&UART5_IRQHandler, /* UART5 Rx and Tx */
(int)&Default_Handler, //(int)&UART6_IRQHandler, /* UART6 Rx and Tx */
(int)&Default_Handler, //(int)&UART7_IRQHandler, /* UART7 Rx and Tx */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
(int)&Default_Handler, //(int)&I2C2_IRQHandler, /* I2C2 Master and Slave */
(int)&Default_Handler, //(int)&I2C3_IRQHandler, /* I2C3 Master and Slave */
(int)&Default_Handler, //(int)&Timer4A_IRQHandler, /* Timer 4 subtimer A */
(int)&Default_Handler, //(int)&Timer4B_IRQHandler, /* Timer 4 subtimer B */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
(int)&Default_Handler, //(int)&Timer5A_IRQHandler, /* Timer 5 subtimer A */
(int)&Default_Handler, //(int)&Timer5B_IRQHandler, /* Timer 5 subtimer B */
(int)&Default_Handler, //(int)&WideTimer0A_IRQHandler, /* Wide Timer 0 subtimer A */
(int)&Default_Handler, //(int)&WideTimer0B_IRQHandler, /* Wide Timer 0 subtimer B */
(int)&Default_Handler, //(int)&WideTimer1A_IRQHandler, /* Wide Timer 1 subtimer A */
(int)&Default_Handler, //(int)&WideTimer1B_IRQHandler, /* Wide Timer 1 subtimer B */
(int)&Default_Handler, //(int)&WideTimer2A_IRQHandler, /* Wide Timer 2 subtimer A */
(int)&Default_Handler, //(int)&WideTimer2B_IRQHandler, /* Wide Timer 2 subtimer B */
(int)&Default_Handler, //(int)&WideTimer3A_IRQHandler, /* Wide Timer 3 subtimer A */
(int)&Default_Handler, //(int)&WideTimer3B_IRQHandler, /* Wide Timer 3 subtimer B */
(int)&Default_Handler, //(int)&WideTimer4A_IRQHandler, /* Wide Timer 4 subtimer A */
(int)&Default_Handler, //(int)&WideTimer4B_IRQHandler, /* Wide Timer 4 subtimer B */
(int)&Default_Handler, //(int)&WideTimer5A_IRQHandler, /* Wide Timer 5 subtimer A */
(int)&Default_Handler, //(int)&WideTimer5B_IRQHandler, /* Wide Timer 5 subtimer B */
(int)&Default_Handler, //(int)&FPU_IRQHandler, /* FPU */
0, /* Reserved */
0, /* Reserved */
(int)&Default_Handler, //(int)&I2C4_IRQHandler, /* I2C4 Master and Slave */
(int)&Default_Handler, //(int)&I2C5_IRQHandler, /* I2C5 Master and Slave */
(int)&Default_Handler, //(int)&GPIOPortM_IRQHandler, /* GPIO Port M */
(int)&Default_Handler, //(int)&GPIOPortN_IRQHandler, /* GPIO Port N */
(int)&Default_Handler, //(int)&QEI2_IRQHandler, /* Quadrature Encoder 2 */
0, /* Reserved */
0, /* Reserved */
(int)&Default_Handler, //(int)&GPIOPortP0_IRQHandler, /* GPIO Port P (Summary or P0) */
(int)&Default_Handler, //(int)&GPIOPortP1_IRQHandler, /* GPIO Port P1 */
(int)&Default_Handler, //(int)&GPIOPortP2_IRQHandler, /* GPIO Port P2 */
(int)&Default_Handler, //(int)&GPIOPortP3_IRQHandler, /* GPIO Port P3 */
(int)&Default_Handler, //(int)&GPIOPortP4_IRQHandler, /* GPIO Port P4 */
(int)&Default_Handler, //(int)&GPIOPortP5_IRQHandler, /* GPIO Port P5 */
(int)&Default_Handler, //(int)&GPIOPortP6_IRQHandler, /* GPIO Port P6 */
(int)&Default_Handler, //(int)&GPIOPortP7_IRQHandler, /* GPIO Port P7 */
(int)&Default_Handler, //(int)&GPIOPortQ0_IRQHandler, /* GPIO Port Q (Summary or Q0) */
(int)&Default_Handler, //(int)&GPIOPortQ1_IRQHandler, /* GPIO Port Q1 */
(int)&Default_Handler, //(int)&GPIOPortQ2_IRQHandler, /* GPIO Port Q2 */
(int)&Default_Handler, //(int)&GPIOPortQ3_IRQHandler, /* GPIO Port Q3 */
(int)&Default_Handler, //(int)&GPIOPortQ4_IRQHandler, /* GPIO Port Q4 */
(int)&Default_Handler, //(int)&GPIOPortQ5_IRQHandler, /* GPIO Port Q5 */
(int)&Default_Handler, //(int)&GPIOPortQ6_IRQHandler, /* GPIO Port Q6 */
(int)&Default_Handler, //(int)&GPIOPortQ7_IRQHandler, /* GPIO Port Q7 */
(int)&Default_Handler, //(int)&GPIOPortR_IRQHandler, /* GPIO Port R */
(int)&Default_Handler, //(int)&GPIOPortS_IRQHandler, /* GPIO Port S */
(int)&Default_Handler, //(int)&PWM1Gen0_IRQHandler, /* PWM 1 Generator 0 */
(int)&Default_Handler, //(int)&PWM1Gen1_IRQHandler, /* PWM 1 Generator 1 */
(int)&Default_Handler, //(int)&PWM1Gen2_IRQHandler, /* PWM 1 Generator 2 */
(int)&Default_Handler, //(int)&PWM1Gen3_IRQHandler, /* PWM 1 Generator 3 */
(int)&Default_Handler, //(int)&PWM1Fault_IRQHandler, /* PWM 1 Fault */
};
//*****************************************************************************
//
// This is the code that gets called when the processor first starts execution
// following a reset event. Only the absolutely necessary set is performed,
// after which the application supplied entry() routine is called. Any fancy
// actions (such as making decisions based on the reset cause register, and
// resetting the bits in that register) are left solely in the hands of the
// application.
//
//*****************************************************************************
void Reset_Handler(void) {
// First, call the CMSIS SystemInit() to set up the CPU clock.
// Next, jump to the CCS C initialization routine. This will enable the
// floating-point unit as well, so that does not need to be done here.
//
__asm volatile(
" .global _c_int00\n\r"
" .global SystemInit\n\r"
" bl.w SystemInit\n\r"
" b.w _c_int00\n\r");
}
/* fault exception handlers ------------------------------------------------*/
void Default_Handler(void) {
__asm volatile (
" .global assert_failed\n\r"
" mov r0,#0\n\r"
" mov r1,#0\n\r"
" b.w assert_failed\n\r"
);
}
/*..........................................................................*/
void NMI_Handler(void) {
__asm(
" .global assert_failed\n\r"
" mov r0,#0\n\r"
" mov r1,#1\n\r"
" b.w assert_failed\n\r"
);
}
/*..........................................................................*/
void MemManage_Handler(void) {
__asm(
" .global assert_failed\n\r"
" mov r0,#0\n\r"
" mov r1,#2\n\r"
" b.w assert_failed\n\r"
);
}
/*..........................................................................*/
void HardFault_Handler(void) {
__asm volatile (
" .global assert_failed\n\r"
" mov r0,#0\n\r"
" mov r1,#3\n\r"
" b.w assert_failed\n\r"
);
}
/*..........................................................................*/
void BusFault_Handler(void) {
__asm volatile (
" .global assert_failed\n\r"
" mov r0,#0\n\r"
" mov r1,#4\n\r"
" b.w assert_failed\n\r"
);
}
/*..........................................................................*/
void UsageFault_Handler(void) {
__asm volatile (
" .global assert_failed\n\r"
" mov r0,#0\n\r"
" mov r1,#5\n\r"
" b.w assert_failed\n\r"
);
}
/*..........................................................................*/
void DebugMon_Handler(void) {
__asm volatile (
" .global assert_failed\n\r"
" mov r0,#0\n\r"
" mov r1,#6\n\r"
" b.w assert_failed\n\r"
);
}
/*..........................................................................*/
void _init(void) { /* dummy */
}
/*..........................................................................*/
void _fini(void) { /* dummy */
}

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<configurations XML_version="1.2" id="configurations_0">
<configuration XML_version="1.2" id="configuration_0">
<instance XML_version="1.2" desc="Stellaris In-Circuit Debug Interface" href="connections/Stellaris_ICDI_Connection.xml" id="Stellaris In-Circuit Debug Interface" xml="Stellaris_ICDI_Connection.xml" xmlpath="connections"/>
<connection XML_version="1.2" id="Stellaris In-Circuit Debug Interface">
<instance XML_version="1.2" href="drivers/stellaris_cs_dap.xml" id="drivers" xml="stellaris_cs_dap.xml" xmlpath="drivers"/>
<instance XML_version="1.2" href="drivers/stellaris_cortex_m4.xml" id="drivers" xml="stellaris_cortex_m4.xml" xmlpath="drivers"/>
<platform XML_version="1.2" id="platform_0">
<instance XML_version="1.2" desc="Tiva TM4C123GH6PM" href="devices/tm4c123gh6pm.xml" id="Tiva TM4C123GH6PM" xml="tm4c123gh6pm.xml" xmlpath="devices"/>
</platform>
</connection>
</configuration>
</configurations>

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The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based
on the device and connection settings specified in your project on the Properties > General page.
Please note that in automatic target-configuration management, changes to the project's device and/or
connection settings will either modify an existing or generate a new target-configuration file. Thus,
if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively,
you may create your own target-configuration file for this project and manage it manually. You can
always switch back to automatic target-configuration management by checking the "Manage the project's
target-configuration automatically" checkbox on the project's Properties > General page.

45
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/******************************************************************************
*
* Default Linker Command file for the Texas Instruments TM4C123GH6PM
*
* This is derived from revision 14351 of the TivaWare Library.
*
*****************************************************************************/
--retain=g_pfnVectors
MEMORY
{
FLASH (RX) : origin = 0x00000000, length = 0x00040000
SRAM (RWX) : origin = 0x20000000, length = 0x00008000
}
/* The following command line options are set as part of the CCS project. */
/* If you are building using the command line, or for some reason want to */
/* define them here, you can uncomment and modify these lines as needed. */
/* If you are using CCS for building, it is probably better to make any such */
/* modifications in your CCS project and leave this file alone. */
/* */
/* --heap_size=0 */
/* --stack_size=256 */
/* --library=rtsv7M4_T_le_eabi.lib */
/* Section allocation in memory */
SECTIONS
{
.intvecs: > 0x00000000
.text : > FLASH
.const : > FLASH
.cinit : > FLASH
.pinit : > FLASH
.init_array : > FLASH
.vtable : > 0x20000000
.data : > SRAM
.bss : > SRAM
.sysmem : > SRAM
.stack : > SRAM
}
__STACK_TOP = __stack + 512;

11
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eclipse.preferences.version=1
encoding//Debug/QP/subdir_rules.mk=UTF-8
encoding//Debug/QP/subdir_vars.mk=UTF-8
encoding//Debug/QP_include/subdir_rules.mk=UTF-8
encoding//Debug/QP_include/subdir_vars.mk=UTF-8
encoding//Debug/QP_port/subdir_rules.mk=UTF-8
encoding//Debug/QP_port/subdir_vars.mk=UTF-8
encoding//Debug/makefile=UTF-8
encoding//Debug/sources.mk=UTF-8
encoding//Debug/subdir_rules.mk=UTF-8
encoding//Debug/subdir_vars.mk=UTF-8

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eclipse.preferences.version=1
encoding//Debug/QP/subdir_rules.mk=UTF-8
encoding//Debug/QP/subdir_vars.mk=UTF-8
encoding//Debug/QP_include/subdir_rules.mk=UTF-8
encoding//Debug/QP_include/subdir_vars.mk=UTF-8
encoding//Debug/QP_port/subdir_rules.mk=UTF-8
encoding//Debug/QP_port/subdir_vars.mk=UTF-8
encoding//Debug/makefile=UTF-8
encoding//Debug/sources.mk=UTF-8
encoding//Debug/subdir_rules.mk=UTF-8
encoding//Debug/subdir_vars.mk=UTF-8

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eclipse.preferences.version=1
encoding//Debug/QP/subdir_rules.mk=UTF-8
encoding//Debug/QP/subdir_vars.mk=UTF-8
encoding//Debug/QP_include/subdir_rules.mk=UTF-8
encoding//Debug/QP_include/subdir_vars.mk=UTF-8
encoding//Debug/makefile=UTF-8
encoding//Debug/sources.mk=UTF-8
encoding//Debug/subdir_rules.mk=UTF-8
encoding//Debug/subdir_vars.mk=UTF-8

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/// @file
/// @brief QEP/C++ port to ARM Cortex-M, generic C++ compiler
/// @cond
///***************************************************************************
/// Last updated for version 5.4.0
/// Last updated on 2015-03-14
///
/// Q u a n t u m L e a P s
/// ---------------------------
/// innovating embedded systems
///
/// Copyright (C) Quantum Leaps, All rights reserved.
///
/// This program is open source software: you can redistribute it and/or
/// modify it under the terms of the GNU General Public License as published
/// by the Free Software Foundation, either version 3 of the License, or
/// (at your option) any later version.
///
/// Alternatively, this program may be distributed and modified under the
/// terms of Quantum Leaps commercial licenses, which expressly supersede
/// the GNU General Public License and are specifically designed for
/// licensees interested in retaining the proprietary status of their code.
///
/// This program is distributed in the hope that it will be useful,
/// but WITHOUT ANY WARRANTY; without even the implied warranty of
/// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
/// GNU General Public License for more details.
///
/// You should have received a copy of the GNU General Public License
/// along with this program. If not, see <http://www.gnu.org/licenses/>.
///
/// Contact information:
/// Web: www.state-machine.com
/// Email: info@state-machine.com
///***************************************************************************
/// @endcond
#ifndef qep_port_h
#define qep_port_h
#include <stdint.h> // Exact-width types. WG14/N843 C99 Standard
#include "qep.h" // QEP platform-independent public interface
#endif // qep_port_h

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///
/// @file
/// @brief QF/C++ port to Cortex-M, preemptive QK kernel, TI-ARM CCS toolset
/// @cond
///***************************************************************************
/// Last updated for version 5.5.1
/// Last updated on 2015-09-30
///
/// Q u a n t u m L e a P s
/// ---------------------------
/// innovating embedded systems
///
/// Copyright (C) Quantum Leaps, www.state-machine.com.
///
/// This program is open source software: you can redistribute it and/or
/// modify it under the terms of the GNU General Public License as published
/// by the Free Software Foundation, either version 3 of the License, or
/// (at your option) any later version.
///
/// Alternatively, this program may be distributed and modified under the
/// terms of Quantum Leaps commercial licenses, which expressly supersede
/// the GNU General Public License and are specifically designed for
/// licensees interested in retaining the proprietary status of their code.
///
/// This program is distributed in the hope that it will be useful,
/// but WITHOUT ANY WARRANTY; without even the implied warranty of
/// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
/// GNU General Public License for more details.
///
/// You should have received a copy of the GNU General Public License
/// along with this program. If not, see <http://www.gnu.org/licenses/>.
///
/// Contact information:
/// Web: www.state-machine.com
/// Email: info@state-machine.com
///***************************************************************************
/// @endcond
#ifndef qf_port_h
#define qf_port_h
// The maximum number of active objects in the application, see NOTE1
#define QF_MAX_ACTIVE 32
// The maximum number of system clock tick rates
#define QF_MAX_TICK_RATE 2
// is the target M3/M4/M7? see NOTE2
#if (defined __TI_TMS470_V7M3__) \
|| (defined __TI_TMS470_V7M4__) \
|| (defined __TI_TMS470_V7M7__)
// BASEPRI limit for QF-aware ISR priorities, see NOTE3
#define QF_BASEPRI (0xFFU >> 2)
// QF-aware ISR priority for CMSIS function NVIC_SetPriority(), NOTE4
#define QF_AWARE_ISR_CMSIS_PRI (QF_BASEPRI >> (8 - __NVIC_PRIO_BITS))
// QF interrupt disable/enable
#define QF_INT_DISABLE() QF_set_BASEPRI(QF_BASEPRI)
#define QF_INT_ENABLE() QF_set_BASEPRI(0U)
// the intrinsic function _norm() generates the CLZ instruction
#define QF_LOG2(n_) ((uint8_t)(32U - _norm(n_)))
// assembly function for setting the BASEPRI register
extern "C" void QF_set_BASEPRI(unsigned basePri);
// not M3/M4/M7, assuming no BASEPRI register or CLZ instruction
#else
// QF interrupt disable/enable
#define QF_INT_DISABLE() __asm(" CPSID I")
#define QF_INT_ENABLE() __asm(" CPSIE I")
// QF-aware ISR priority for CMSIS function NVIC_SetPriority(), NOTE5
#define QF_AWARE_ISR_CMSIS_PRI 0
#endif // not M3/M4/M7
// QF critical section entry/exit...
// QF_CRIT_STAT_TYPE not defined: "unconditional interrupt disabling" policy
#define QF_CRIT_ENTRY(dummy) QF_INT_DISABLE()
#define QF_CRIT_EXIT(dummy) QF_INT_ENABLE()
#define QF_CRIT_EXIT_NOP() __asm(" NOP")
#include "qep_port.h" // QEP port
#include "qk_port.h" // QK preemptive kernel port
#include "qf.h" // QF platform-independent public interface
//****************************************************************************
// NOTE1:
// The maximum number of active objects QF_MAX_ACTIVE can be increased
// up to 63, if necessary. Here it is set to a lower level to save some RAM.
//
// NOTE2:
// On Cortex-M3/M4/M7, the interrupt disable/enable policy uses the BASEPRI
// register (which is not implemented in Cortex-M0/M0+/M1) to disable
// interrupts only with priority lower than the level specified by the
// QF_BASEPRI macro. The interrupts with priorities above QF_BASEPRI (i.e.,
// with numerical priority values lower than QF_BASEPRI) are not disabled in
// this method. These free-running interrupts are not allowed to call any QF
// services, because QF is not aware of these interrupts. Coversely, only
// "QF-aware" interrupts, with numerical values of priorities eqal to or
// higher than QF_BASEPRI, can call QF services.
//
// NOTE3:
// For Cortex-M3/M4/M7, the macro QF_BASEPRI leaves the top 2 priority bits
// empty for QF-aware interrupts. This is the highest-possible priority
// (lowest possible numerical value) for the guaranteed 3 priority bits
// implemented in the NVIC.
//
// NOTE4:
// The QF_AWARE_ISR_CMSIS_PRI macro is useful as an offset for enumerating
// the QF-aware interrupt priority levels in the applications, whereas the
// numerical values of the QF-aware interrupts must be greater or equal to
// QF_AWARE_ISR_CMSIS_PRI. The enumerated values based on
// QF_AWARE_ISR_CMSIS_PRI can be passed directly to the CMSIS function
// NVIC_SetPriority(), which shifts them by (8 - __NVIC_PRIO_BITS) into the
// correct bit position, while __NVIC_PRIO_BITS is the CMSIS macro defining
// the number of implemented priority bits in the NVIC. Please note that
// the macro QF_AWARE_ISR_CMSIS_PRI is intended only for applications and
// is not used inside the QF port, which remains generic and not dependent
// on the number of implemented priority bits in the NVIC.
//
// NOTE5:
// On Cortex-M0/M0+/M1 (architecture v6-M, v6S-M), the interrupt disabling
// policy uses the PRIMASK register to disable interrupts globally. The
// QF_AWARE_ISR_CMSIS_PRI level is zero, meaning that all interrupts are
// "kernel-aware".
//
#endif // qf_port_h

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/// @file
/// @brief QK/C++ port to ARM Cortex-M, preemptive QK kernel, IAR-ARM toolset
/// @cond
///***************************************************************************
/// Last updated for version 5.4.0
/// Last updated on 2015-05-04
///
/// Q u a n t u m L e a P s
/// ---------------------------
/// innovating embedded systems
///
/// Copyright (C) Quantum Leaps, www.state-machine.com.
///
/// This program is open source software: you can redistribute it and/or
/// modify it under the terms of the GNU General Public License as published
/// by the Free Software Foundation, either version 3 of the License, or
/// (at your option) any later version.
///
/// Alternatively, this program may be distributed and modified under the
/// terms of Quantum Leaps commercial licenses, which expressly supersede
/// the GNU General Public License and are specifically designed for
/// licensees interested in retaining the proprietary status of their code.
///
/// This program is distributed in the hope that it will be useful,
/// but WITHOUT ANY WARRANTY; without even the implied warranty of
/// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
/// GNU General Public License for more details.
///
/// You should have received a copy of the GNU General Public License
/// along with this program. If not, see <http://www.gnu.org/licenses/>.
///
/// Contact information:
/// Web: www.state-machine.com
/// Email: info@state-machine.com
///***************************************************************************
/// @endcond
#ifndef qk_port_h
#define qk_port_h
// QK interrupt entry and exit
#define QK_ISR_ENTRY() do { \
QF_INT_DISABLE(); \
++QK_intNest_; \
QF_INT_ENABLE(); \
} while (0)
#define QK_ISR_EXIT() do { \
QF_INT_DISABLE(); \
--QK_intNest_; \
*Q_UINT2PTR_CAST(uint32_t, 0xE000ED04U) \
= static_cast<uint32_t>(0x10000000U); \
QF_INT_ENABLE(); \
} while (0)
#include "qk.h" // QK platform-independent public interface
#endif // qk_port_h

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;*****************************************************************************
; Product: QK port to ARM Cortex-M (M0,M0+,M1,M3,M4,M7), TI-ARM assembler
; Last Updated for Version: 5.5.1
; Date of the Last Update: 2015-09-30
;
; Q u a n t u m L e a P s
; ---------------------------
; innovating embedded systems
;
; Copyright (C) Quantum Leaps, LLC. All rights reserved.
;
; This program is open source software: you can redistribute it and/or
; modify it under the terms of the GNU General Public License as published
; by the Free Software Foundation, either version 3 of the License, or
; (at your option) any later version.
;
; Alternatively, this program may be distributed and modified under the
; terms of Quantum Leaps commercial licenses, which expressly supersede
; the GNU General Public License and are specifically designed for
; licensees interested in retaining the proprietary status of their code.
;
; This program is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program. If not, see <http://www.gnu.org/licenses/>.
;
; Contact information:
; http://www.state-machine.com
; mailto:info@state-machine.com
;*****************************************************************************
.text
.thumb
.global QK_init
.global PendSV_Handler ; CMSIS-compliant PendSV exception name
.global SVC_Handler ; CMSIS-compliant SVC exception name
.global QF_set_BASEPRI ; set BASEPRI register
.global assert_failed ; low-level assert handler
.ref QK_schedPrio_ ; external reference
.ref QK_sched_ ; external reference
.ref Q_onAssert ; external reference
.ref __STACK_TOP ; external reference
;*****************************************************************************
; The QK_init function sets the priorities of PendSV and SVCall exceptions
; to 0xFF and 0x00, respectively. The function internally disables
; interrupts, but restores the original interrupt lock before exit.
;*****************************************************************************
QK_init: .asmfunc
MRS r0,PRIMASK ; store the state of the PRIMASK in r0
CPSID i ; disable interrupts (set PRIMASK)
LDR r1,SHPR_addr ; System Handler Priority Register
LDR r2,[r1,#8] ; load the System 12-15 Priority Register
MOVS r3,#0xFF
LSLS r3,r3,#16
ORRS r2,r3 ; set PRI_14 (PendSV) to 0xFF
STR r2,[r1,#8] ; write the System 12-15 Priority Register
LDR r2,[r1,#4] ; load the System 8-11 Priority Register
LSLS r3,r3,#8
BICS r2,r3 ; set PRI_11 (SVCall) to 0x00
STR r2,[r1,#4] ; write the System 8-11 Priority Register
MSR PRIMASK,r0 ; restore the original PRIMASK
BX lr ; return to the caller
SHPR_addr: .word 0E000ED18h
.endasmfunc
;*****************************************************************************
; The PendSV_Handler exception handler is used for handling asynchronous
; preemption in QK. The use of the PendSV exception is the recommended
; and most efficient method for performing context switches with ARM Cortex-M.
;
; The PendSV exception should have the lowest priority in the whole system
; (0xFF, see QK_init). All other exceptions and interrupts should have higher
; priority. For example, for NVIC with 2 priority bits all interrupts and
; exceptions must have numerical value of priority lower than 0xC0. In this
; case the interrupt priority levels available to your applications are (in
; the order from the lowest urgency to the highest urgency): 0x80, 0x40, 0x00.
;
; Also, *all* ISRs in the QK application must trigger the PendSV exception
; by calling the QK_ISR_EXIT() macro.
;
; Due to tail-chaining and its lowest priority, the PendSV exception will be
; entered immediately after the exit from the *last* nested interrupt (or
; exception). In QK, this is exactly the time when the QK scheduler needs to
; check for the asynchronous preemption.
;*****************************************************************************
PendSV_Handler: .asmfunc
.if __TI_TMS470_V7M3__ | __TI_TMS470_V7M4__ ; | __TI_TMS470_V7M7__
.if __TI_VFP_SUPPORT__ ; If FPU used...
PUSH {r0,lr} ; push lr (EXC_RETURN) plus stack "aligner"
.endif ; FPU
MOVS r0,#(0xFF >> 2) ; NOTE: Must match QF_BASEPRI in qf_port.h!
MSR BASEPRI,r0 ; selectively disable interrupts
.else ; M0/M0+/M1
CPSIE i ; disable interrupts (set PRIMASK)
.endif ; M0/M0+/M1
BL QK_schedPrio_ ; check if we have preemption
CMP r0,#0 ; is prio == 0 ?
BNE.N scheduler ; if prio != 0, branch to scheduler
.if __TI_TMS470_V7M3__ | __TI_TMS470_V7M4__ ; | __TI_TMS470_V7M7__
; NOTE: r0 == 0 at this point
MSR BASEPRI,r0 ; enable interrupts (clear BASEPRI)
.if __TI_VFP_SUPPORT__ ; If FPU used...
POP {r0,pc} ; pop stack "aligner" and EXC_RETURN to PC
.endif ; FPU
.else ; M0/M0+/M1
CPSIE i ; enable interrupts (clear PRIMASK)
MOVS r0,#6
MVNS r0,r0 ; r0 := ~6 == 0xFFFFFFF9
BX r0 ; exception-return to the task
.endif ; M0/M0+/M1
scheduler:
MOVS r3,#1
LSLS r3,r3,#24 ; r3:=(1 << 24), set the T bit (new xpsr)
LDR r2,QK_sched_addr ; address of the QK scheduler (new pc)
LDR r1,svc_ret_addr ; return address after the call (new lr)
PUSH {r1-r3} ; push xpsr,pc,lr
SUB sp,sp,#(4*4) ; don't care for r12,r3,r2,r1
PUSH {r0} ; push the prio argument (new r0)
MOVS r0,#6
MVNS r0,r0 ; r0 := ~6 == 0xFFFFFFF9
BX r0 ; exception-return to the QK scheduler
svc_ret:
.if __TI_TMS470_V7M3__ | __TI_TMS470_V7M4__ ; | __TI_TMS470_V7M7__
MOVS r0,#0
MSR BASEPRI,r0 ; enable interrupts (clear BASEPRI)
.if __TI_VFP_SUPPORT__ ; If FPU used...
MRS r0,CONTROL ; r0 := CONTROL
BICS r0,r0,#4 ; r0 := r0 & ~4 (FPCA bit)
MSR CONTROL,r0 ; CONTROL := r0 (clear CONTROL[2] FPCA bit)
.endif ; FPU
.else ; M0/M0+/M1
CPSIE i ; enable interrupts at processor level
.endif ; M0/M0+/M1
SVC #0 ; cause SV exception to return to preempted task
QK_sched_addr .word QK_sched_
svc_ret_addr .word svc_ret
.endasmfunc
;*****************************************************************************
; The SVC_Handler exception handler is used for returning back to the
; preempted task. The SVCall exception simply removes its own interrupt
; stack frame from the stack and returns to the preempted task using the
; interrupt stack frame that must be at the top of the stack.
;*****************************************************************************
SVC_Handler: .asmfunc
ADD sp,sp,#(8*4) ; remove one 8-register exception frame
.if __TI_VFP_SUPPORT__ ; If FPU used...
POP {r0,pc} ; pop stack "aligner" and the EXC_RETURN to PC
.else ; no FPU
MOVS r0,#6
MVNS r0,r0 ; r0 := ~6 == 0xFFFFFFF9
BX r0 ; return to the preempted task
.endif ; no FPU
.endasmfunc
;*****************************************************************************
; The QF_set_BASEPRI function sets the BASEPRI register to the value
; passed in r0.
; C prototype: void QF_set_BASEPRI(unsigned basePri);
;*****************************************************************************
QF_set_BASEPRI: .asmfunc
MSR BASEPRI,r0 ; set BASEPRI
BX lr ; return to the caller
.endasmfunc
;*****************************************************************************
; The assert_failed() function restores the SP (in case stack is corrupted)
; and calls Q_onAssert(module, loc)
; C prototype: void assert_failed(char const *module, int loc);
;*****************************************************************************
assert_failed: .asmfunc
LDR sp,STACK_TOP_addr
B.w Q_onAssert
STACK_TOP_addr .word __STACK_TOP
.endasmfunc

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/// @file
/// @brief QS/C++ port to ARM Cortex-M, generic compiler
/// @cond
///***************************************************************************
/// Last updated for version 5.4.0
/// Last updated on 2015-03-14
///
/// Q u a n t u m L e a P s
/// ---------------------------
/// innovating embedded systems
///
/// Copyright (C) Quantum Leaps, www.state-machine.com.
///
/// This program is open source software: you can redistribute it and/or
/// modify it under the terms of the GNU General Public License as published
/// by the Free Software Foundation, either version 3 of the License, or
/// (at your option) any later version.
///
/// Alternatively, this program may be distributed and modified under the
/// terms of Quantum Leaps commercial licenses, which expressly supersede
/// the GNU General Public License and are specifically designed for
/// licensees interested in retaining the proprietary status of their code.
///
/// This program is distributed in the hope that it will be useful,
/// but WITHOUT ANY WARRANTY; without even the implied warranty of
/// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
/// GNU General Public License for more details.
///
/// You should have received a copy of the GNU General Public License
/// along with this program. If not, see <http://www.gnu.org/licenses/>.
///
/// Contact information:
/// Web: www.state-machine.com
/// Email: info@state-machine.com
///***************************************************************************
/// @endcond
#ifndef qs_port_h
#define qs_port_h
#define QS_TIME_SIZE 4
#define QS_OBJ_PTR_SIZE 4
#define QS_FUN_PTR_SIZE 4
//****************************************************************************
// NOTE: QS might be used with or without other QP components, in which case
// the separate definitions of the macros Q_ROM, Q_ROM_VAR,
// QF_CRIT_STAT_TYPE, QF_CRIT_ENTRY, and QF_CRIT_EXIT are needed. In this
// port QS is configured to be used with the QF framework component, by
// simply including "qf_port.h" *before* "qs.h".
//
#include "qf_port.h" // use QS with QF
#include "qs.h" // QS platform-independent public interface
#endif // qs_port_h

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/// @file
/// @brief QEP/C++ port to ARM Cortex-M, generic C++ compiler
/// @cond
///***************************************************************************
/// Last updated for version 5.4.0
/// Last updated on 2015-03-14
///
/// Q u a n t u m L e a P s
/// ---------------------------
/// innovating embedded systems
///
/// Copyright (C) Quantum Leaps, All rights reserved.
///
/// This program is open source software: you can redistribute it and/or
/// modify it under the terms of the GNU General Public License as published
/// by the Free Software Foundation, either version 3 of the License, or
/// (at your option) any later version.
///
/// Alternatively, this program may be distributed and modified under the
/// terms of Quantum Leaps commercial licenses, which expressly supersede
/// the GNU General Public License and are specifically designed for
/// licensees interested in retaining the proprietary status of their code.
///
/// This program is distributed in the hope that it will be useful,
/// but WITHOUT ANY WARRANTY; without even the implied warranty of
/// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
/// GNU General Public License for more details.
///
/// You should have received a copy of the GNU General Public License
/// along with this program. If not, see <http://www.gnu.org/licenses/>.
///
/// Contact information:
/// Web: www.state-machine.com
/// Email: info@state-machine.com
///***************************************************************************
/// @endcond
#ifndef qep_port_h
#define qep_port_h
#include <stdint.h> // Exact-width types. WG14/N843 C99 Standard
#include "qep.h" // QEP platform-independent public interface
#endif // qep_port_h

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///
/// @file
/// @brief QF/C++ port to Cortex-M, cooperative QV kernel, TI-ARM CCS toolset
/// @cond
///***************************************************************************
/// Last updated for version 5.5.1
/// Last updated on 2015-09-30
///
/// Q u a n t u m L e a P s
/// ---------------------------
/// innovating embedded systems
///
/// Copyright (C) Quantum Leaps, www.state-machine.com.
///
/// This program is open source software: you can redistribute it and/or
/// modify it under the terms of the GNU General Public License as published
/// by the Free Software Foundation, either version 3 of the License, or
/// (at your option) any later version.
///
/// Alternatively, this program may be distributed and modified under the
/// terms of Quantum Leaps commercial licenses, which expressly supersede
/// the GNU General Public License and are specifically designed for
/// licensees interested in retaining the proprietary status of their code.
///
/// This program is distributed in the hope that it will be useful,
/// but WITHOUT ANY WARRANTY; without even the implied warranty of
/// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
/// GNU General Public License for more details.
///
/// You should have received a copy of the GNU General Public License
/// along with this program. If not, see <http://www.gnu.org/licenses/>.
///
/// Contact information:
/// Web: www.state-machine.com
/// Email: info@state-machine.com
///***************************************************************************
/// @endcond
#ifndef qf_port_h
#define qf_port_h
// The maximum number of active objects in the application, see NOTE1
#define QF_MAX_ACTIVE 32
// The maximum number of system clock tick rates
#define QF_MAX_TICK_RATE 2
// is the target M3/M4/M7? see NOTE2
#if (defined __TI_TMS470_V7M3__) \
|| (defined __TI_TMS470_V7M4__) \
|| (defined __TI_TMS470_V7M7__)
// BASEPRI limit for QF-aware ISR priorities, see NOTE3
#define QF_BASEPRI (0xFFU >> 2)
// QF-aware ISR priority for CMSIS function NVIC_SetPriority(), NOTE4
#define QF_AWARE_ISR_CMSIS_PRI (QF_BASEPRI >> (8 - __NVIC_PRIO_BITS))
// QF interrupt disable/enable
#define QF_INT_DISABLE() QF_set_BASEPRI(QF_BASEPRI)
#define QF_INT_ENABLE() QF_set_BASEPRI(0U)
// the intrinsic function _norm() generates the CLZ instruction
#define QF_LOG2(n_) ((uint8_t)(32U - _norm(n_)))
// assembly function for setting the BASEPRI register
extern "C" void QF_set_BASEPRI(unsigned basePri);
// not M3/M4/M7, assuming no BASEPRI register or CLZ instruction
#else
// QF interrupt disable/enable
#define QF_INT_DISABLE() __asm(" CPSID I")
#define QF_INT_ENABLE() __asm(" CPSIE I")
// QF-aware ISR priority for CMSIS function NVIC_SetPriority(), NOTE5
#define QF_AWARE_ISR_CMSIS_PRI 0
#endif // not M3/M4/M7
// QF critical section entry/exit...
// QF_CRIT_STAT_TYPE not defined: "unconditional interrupt disabling" policy
#define QF_CRIT_ENTRY(dummy) QF_INT_DISABLE()
#define QF_CRIT_EXIT(dummy) QF_INT_ENABLE()
#define QF_CRIT_EXIT_NOP() __asm(" NOP")
#include "qep_port.h" // QEP port
#include "qv_port.h" // QV port cooperative kernel port
#include "qf.h" // QF platform-independent public interface
//****************************************************************************
// NOTE1:
// The maximum number of active objects QF_MAX_ACTIVE can be increased
// up to 63, if necessary. Here it is set to a lower level to save some RAM.
//
// NOTE2:
// On Cortex-M3/M4/M7, the interrupt disable/enable policy uses the BASEPRI
// register (which is not implemented in Cortex-M0/M0+/M1) to disable
// interrupts only with priority lower than the level specified by the
// QF_BASEPRI macro. The interrupts with priorities above QF_BASEPRI (i.e.,
// with numerical priority values lower than QF_BASEPRI) are not disabled in
// this method. These free-running interrupts are not allowed to call any QF
// services, because QF is not aware of these interrupts. Coversely, only
// "QF-aware" interrupts, with numerical values of priorities eqal to or
// higher than QF_BASEPRI, can call QF services.
//
// NOTE3:
// For Cortex-M3/M4/M7, the macro QF_BASEPRI leaves the top 2 priority bits
// empty for QF-aware interrupts. This is the highest-possible priority
// (lowest possible numerical value) for the guaranteed 3 priority bits
// implemented in the NVIC.
//
// NOTE4:
// The QF_AWARE_ISR_CMSIS_PRI macro is useful as an offset for enumerating
// the QF-aware interrupt priority levels in the applications, whereas the
// numerical values of the QF-aware interrupts must be greater or equal to
// QF_AWARE_ISR_CMSIS_PRI. The enumerated values based on
// QF_AWARE_ISR_CMSIS_PRI can be passed directly to the CMSIS function
// NVIC_SetPriority(), which shifts them by (8 - __NVIC_PRIO_BITS) into the
// correct bit position, while __NVIC_PRIO_BITS is the CMSIS macro defining
// the number of implemented priority bits in the NVIC. Please note that
// the macro QF_AWARE_ISR_CMSIS_PRI is intended only for applications and
// is not used inside the QF port, which remains generic and not dependent
// on the number of implemented priority bits in the NVIC.
//
// NOTE5:
// On Cortex-M0/M0+/M1 (architecture v6-M, v6S-M), the interrupt disabling
// policy uses the PRIMASK register to disable interrupts globally. The
// QF_AWARE_ISR_CMSIS_PRI level is zero, meaning that all interrupts are
// "kernel-aware".
//
#endif // qf_port_h

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/// @file
/// @brief QS/C++ port to ARM Cortex-M, generic compiler
/// @cond
///***************************************************************************
/// Last updated for version 5.4.0
/// Last updated on 2015-03-14
///
/// Q u a n t u m L e a P s
/// ---------------------------
/// innovating embedded systems
///
/// Copyright (C) Quantum Leaps, www.state-machine.com.
///
/// This program is open source software: you can redistribute it and/or
/// modify it under the terms of the GNU General Public License as published
/// by the Free Software Foundation, either version 3 of the License, or
/// (at your option) any later version.
///
/// Alternatively, this program may be distributed and modified under the
/// terms of Quantum Leaps commercial licenses, which expressly supersede
/// the GNU General Public License and are specifically designed for
/// licensees interested in retaining the proprietary status of their code.
///
/// This program is distributed in the hope that it will be useful,
/// but WITHOUT ANY WARRANTY; without even the implied warranty of
/// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
/// GNU General Public License for more details.
///
/// You should have received a copy of the GNU General Public License
/// along with this program. If not, see <http://www.gnu.org/licenses/>.
///
/// Contact information:
/// Web: www.state-machine.com
/// Email: info@state-machine.com
///***************************************************************************
/// @endcond
#ifndef qs_port_h
#define qs_port_h
#define QS_TIME_SIZE 4
#define QS_OBJ_PTR_SIZE 4
#define QS_FUN_PTR_SIZE 4
//****************************************************************************
// NOTE: QS might be used with or without other QP components, in which case
// the separate definitions of the macros Q_ROM, Q_ROM_VAR,
// QF_CRIT_STAT_TYPE, QF_CRIT_ENTRY, and QF_CRIT_EXIT are needed. In this
// port QS is configured to be used with the QF framework component, by
// simply including "qf_port.h" *before* "qs.h".
//
#include "qf_port.h" // use QS with QF
#include "qs.h" // QS platform-independent public interface
#endif // qs_port_h

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///
/// @file
/// @brief QV/C++ port to ARM Cortex-M, TI-ARM (CCS) toolset
/// @cond
///***************************************************************************
/// Last updated for version 5.4.0
/// Last updated on 2015-05-04
///
/// Q u a n t u m L e a P s
/// ---------------------------
/// innovating embedded systems
///
/// Copyright (C) Quantum Leaps, www.state-machine.com.
///
/// This program is open source software: you can redistribute it and/or
/// modify it under the terms of the GNU General Public License as published
/// by the Free Software Foundation, either version 3 of the License, or
/// (at your option) any later version.
///
/// Alternatively, this program may be distributed and modified under the
/// terms of Quantum Leaps commercial licenses, which expressly supersede
/// the GNU General Public License and are specifically designed for
/// licensees interested in retaining the proprietary status of their code.
///
/// This program is distributed in the hope that it will be useful,
/// but WITHOUT ANY WARRANTY; without even the implied warranty of
/// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
/// GNU General Public License for more details.
///
/// You should have received a copy of the GNU General Public License
/// along with this program. If not, see <http://www.gnu.org/licenses/>.
///
/// Contact information:
/// Web: www.state-machine.com
/// Email: info@state-machine.com
///***************************************************************************
/// @endcond
#ifndef qv_port_h
#define qv_port_h
#if (defined __TI_TMS470_V7M3__) || (defined __TI_TMS470_V7M4__)
// macro to put the CPU to sleep inside QV_onIdle()
#define QV_CPU_SLEEP() do { \
__asm(" CPSID I"); \
QF_INT_ENABLE(); \
__asm(" WFI"); \
__asm(" CPSIE I"); \
} while (false)
#else // not M3 or M4
// macro to put the CPU to sleep inside QV_onIdle()
#define QV_CPU_SLEEP() do { \
__asm(" WFI"); \
QF_INT_ENABLE(); \
} while (false)
#endif
#include "qv.h" // QV platform-independent public interface
#endif // qv_port_h

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;*****************************************************************************
; Product: QV port to ARM Cortex-M (M0,M0+,M1,M3,M4,M7), TI-ARM assembler
; Last Updated for Version: 5.5.1
; Date of the Last Update: 2015-09-30
;
; Q u a n t u m L e a P s
; ---------------------------
; innovating embedded systems
;
; Copyright (C) Quantum Leaps, LLC. All rights reserved.
;
; This program is open source software: you can redistribute it and/or
; modify it under the terms of the GNU General Public License as published
; by the Free Software Foundation, either version 3 of the License, or
; (at your option) any later version.
;
; Alternatively, this program may be distributed and modified under the
; terms of Quantum Leaps commercial licenses, which expressly supersede
; the GNU General Public License and are specifically designed for
; licensees interested in retaining the proprietary status of their code.
;
; This program is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program. If not, see <http://www.gnu.org/licenses/>.
;
; Contact information:
; http://www.state-machine.com
; mailto:info@state-machine.com
;*****************************************************************************
.text
.thumb
.global QF_set_BASEPRI ; set BASEPRI register
.global assert_failed ; low-level assert handler
.ref Q_onAssert ; external reference
.ref __STACK_TOP ; external reference
;*****************************************************************************
; The QF_set_BASEPRI function sets the BASEPRI register to the value
; passed in r0.
; C prototype: void QF_set_BASEPRI(uint32_t basePri);
;*****************************************************************************
QF_set_BASEPRI: .asmfunc
MSR BASEPRI,r0 ; set BASEPRI
BX lr ; return to the caller
.endasmfunc
;*****************************************************************************
; The assert_failed() function restores the SP (in case stack is corrupted)
; and calls Q_onAssert(module, loc)
; C prototype: void assert_failed(char const *module, int loc);
;*****************************************************************************
assert_failed: .asmfunc
LDR sp,STACK_TOP_addr
B.w Q_onAssert
STACK_TOP_addr .word __STACK_TOP
.endasmfunc