diff --git a/examples/arm-cm/dpp_efm32-slstk3401a/qk/armclang/dpp-qk.uvprojx b/examples/arm-cm/dpp_efm32-slstk3401a/qk/armclang/dpp-qk.uvprojx
index 4f1e2ffa..b67d63c3 100644
--- a/examples/arm-cm/dpp_efm32-slstk3401a/qk/armclang/dpp-qk.uvprojx
+++ b/examples/arm-cm/dpp_efm32-slstk3401a/qk/armclang/dpp-qk.uvprojx
@@ -337,7 +337,7 @@
0
QK_USE_IRQ_NUM=25 QK_USE_IRQ_HANDLER=CRYPTO_IRQHandler
+ QK_USE_IRQ_NUM=33 QK_USE_IRQ_HANDLER=FPUEH_IRQHandler
..\..;..\..\..\..\..\include;..\..\..\..\..\ports\arm-cm\qk\armclang;..\..\..\..\..\3rd_party\CMSIS\Include;..\..\..\..\..\3rd_party\efm32pg1b
diff --git a/examples/arm-cm/dpp_efm32-slstk3401a/qk/gnu/Makefile b/examples/arm-cm/dpp_efm32-slstk3401a/qk/gnu/Makefile
index f15026f6..28300826 100644
--- a/examples/arm-cm/dpp_efm32-slstk3401a/qk/gnu/Makefile
+++ b/examples/arm-cm/dpp_efm32-slstk3401a/qk/gnu/Makefile
@@ -1,13 +1,13 @@
##############################################################################
# Product: Makefile for QP/C++ on EMF32-SLSTK3401A, QK kernel, GNU-ARM
-# Last Updated for Version: 7.0.1
-# Date of the Last Update: 2022-05-23
+# Last Updated for Version: 7.2.1
+# Date of the Last Update: 2023-01-14
#
# Q u a n t u m L e a P s
# ------------------------
# Modern Embedded Software
#
-# Copyright (C) 2005-2021 Quantum Leaps, LLC. All rights reserved.
+# Copyright (C) 2005 Quantum Leaps, LLC. All rights reserved.
#
# This program is open source software: you can redistribute it and/or
# modify it under the terms of the GNU General Public License as published
@@ -45,7 +45,7 @@
# NOTE:
# To use this Makefile on Windows, you will need the GNU make utility, which
# is included in the Qtools collection for Windows, see:
-# http://sourceforge.net/projects/qpc/files/Qtools/
+# https://github.com/QuantumLeaps/qtools/releases
#
#-----------------------------------------------------------------------------
@@ -138,8 +138,8 @@ LIBS :=
# defines
DEFINES := -DEFM32PG1B200F256GM48=1 \
- -DQK_USE_IRQ_HANDLER=CRYPTO_IRQHandler \
- -DQK_USE_IRQ_NUM=25
+ -DQK_USE_IRQ_NUM=33 \
+ -DQK_USE_IRQ_HANDLER=FPUEH_IRQHandler
# ARM CPU, ARCH, FPU, and Float-ABI types...
# ARM_CPU: [cortex-m0 | cortex-m0plus | cortex-m1 | cortex-m3 | cortex-m4]
@@ -180,7 +180,7 @@ MKDIR := mkdir
RM := rm
#-----------------------------------------------------------------------------
-# build options for various configurations for ARM Cortex-M4F
+# build options for various configurations for ARM Cortex-M
#
# combine all the soruces...
diff --git a/examples/arm-cm/dpp_efm32-slstk3401a/qk/gnu/Makefile-cpp20 b/examples/arm-cm/dpp_efm32-slstk3401a/qk/gnu/Makefile-cpp20
index e5026436..12b72ea6 100644
--- a/examples/arm-cm/dpp_efm32-slstk3401a/qk/gnu/Makefile-cpp20
+++ b/examples/arm-cm/dpp_efm32-slstk3401a/qk/gnu/Makefile-cpp20
@@ -1,13 +1,13 @@
##############################################################################
# Product: Makefile for QP/C++ on EMF32-SLSTK3401A, QK kernel, GNU-ARM
-# Last Updated for Version: 7.0.0
-# Date of the Last Update: 2022-05-13
+# Last Updated for Version: 7.2.1
+# Date of the Last Update: 2023-01-14
#
# Q u a n t u m L e a P s
# ------------------------
# Modern Embedded Software
#
-# Copyright (C) 2005-2022 Quantum Leaps, LLC. All rights reserved.
+# Copyright (C) 2005 Quantum Leaps, LLC. All rights reserved.
#
# This program is open source software: you can redistribute it and/or
# modify it under the terms of the GNU General Public License as published
@@ -80,7 +80,6 @@ VPATH = \
INCLUDES = \
-I../.. \
-I$(QPCPP)/include \
- -I$(QPCPP)/src \
-I$(QP_PORT_DIR) \
-I$(QPCPP)/3rd_party/CMSIS/Include \
-I$(QPCPP)/3rd_party/efm32pg1b
@@ -139,8 +138,8 @@ LIBS :=
# defines
DEFINES := -DEFM32PG1B200F256GM48=1 \
- -DQK_USE_IRQ_NUM=25 \
- -DQK_USE_IRQ_HANDLER=CRYPTO_IRQHandler
+ -DQK_USE_IRQ_NUM=33 \
+ -DQK_USE_IRQ_HANDLER=FPUEH_IRQHandler
# ARM CPU, ARCH, FPU, and Float-ABI types...
# ARM_CPU: [cortex-m0 | cortex-m0plus | cortex-m1 | cortex-m3 | cortex-m4]
diff --git a/examples/arm-cm/dpp_efm32-slstk3401a/qk/iar/dpp-qk.ewp b/examples/arm-cm/dpp_efm32-slstk3401a/qk/iar/dpp-qk.ewp
index 29f3d3cb..b297f857 100644
--- a/examples/arm-cm/dpp_efm32-slstk3401a/qk/iar/dpp-qk.ewp
+++ b/examples/arm-cm/dpp_efm32-slstk3401a/qk/iar/dpp-qk.ewp
@@ -215,8 +215,8 @@
CCDefines
EFM32PG1B200F256GM48
- QK_USE_IRQ_HANDLER=CRYPTO_IRQHandler
- QK_USE_IRQ_NUM=25
+ QK_USE_IRQ_HANDLER=FPUEH_IRQHandler
+ QK_USE_IRQ_NUM=33
CCPreprocFile
@@ -3258,255 +3258,6 @@
QP_port
$PROJ_DIR$\..\..\..\..\..\ports\arm-cm\qk\iar\qk_port.cpp
-
- Debug
-
- ICCARM
-
- 37
- 0
- 1
-
- CCOptimizationNoSizeConstraints
- 0
-
-
- CCDefines
- EFM32PG1B200F256GM48
- QK_USE_IRQ_NUM=25
- QK_USE_IRQ_HANDLER=CRYPTO_IRQHandler
-
-
- CCPreprocFile
- 0
-
-
- CCPreprocComments
- 0
-
-
- CCPreprocLine
- 0
-
-
- CCListCFile
- 0
-
-
- CCListCMnemonics
- 0
-
-
- CCListCMessages
- 0
-
-
- CCListAssFile
- 0
-
-
- CCListAssSource
- 0
-
-
- CCEnableRemarks
- 0
-
-
- CCDiagSuppress
- Pe540
-
-
- CCDiagRemark
-
-
- CCDiagWarning
-
-
- CCDiagError
-
-
- CCObjPrefix
- 1
-
-
- CCAllowList
- 1
- 00000000
-
-
- CCDebugInfo
- 1
-
-
- IEndianMode
- 1
-
-
- IProcessor
- 1
-
-
- IExtraOptionsCheck
- 1
-
-
- IExtraOptions
- --enable_restrict
-
-
- CCLangConformance
- 0
-
-
- CCSignedPlainChar
- 1
-
-
- CCRequirePrototypes
- 1
-
-
- CCDiagWarnAreErr
- 0
-
-
- CCCompilerRuntimeInfo
- 0
-
-
- IFpuProcessor
- 1
-
-
- OutputFile
- $FILE_BNAME$.o
-
-
- CCLibConfigHeader
- 1
-
-
- PreInclude
-
-
- CCIncludePath2
- $PROJ_DIR$\..
- $PROJ_DIR$\..\..
- $PROJ_DIR$\..\..\..\..\..\include
- $PROJ_DIR$\..\..\..\..\..\ports\arm-cm\qk\iar
- $PROJ_DIR$\..\..\..\..\..\3rd_party\CMSIS\Include
- $PROJ_DIR$\..\..\..\..\..\3rd_party\efm32pg1b
-
-
- CCStdIncCheck
- 0
-
-
- CCCodeSection
- .text
-
-
- IProcessorMode2
- 1
-
-
- CCOptLevel
- 1
-
-
- CCOptStrategy
- 0
- 1
-
-
- CCOptLevelSlave
- 1
-
-
- CCPosIndRopi
- 0
-
-
- CCPosIndRwpi
- 0
-
-
- CCPosIndNoDynInit
- 0
-
-
- IccLang
- 2
-
-
- IccCDialect
- 1
-
-
- IccAllowVLA
- 0
-
-
- IccStaticDestr
- 1
-
-
- IccCppInlineSemantics
- 1
-
-
- IccCmsis
- 1
-
-
- IccFloatSemantics
- 0
-
-
- CCNoLiteralPool
- 0
-
-
- CCOptStrategySlave
- 0
- 1
-
-
- CCEncSource
- 0
-
-
- CCEncOutput
- 0
-
-
- CCEncOutputBom
- 1
-
-
- CCEncInput
- 0
-
-
- IccExceptions2
- 0
-
-
- IccRTTI2
- 0
-
-
- CCStackProtection
- 0
-
-
-
-
diff --git a/examples/arm-cm/dpp_efm32-slstk3401a/qxk/armclang/dpp-qxk.uvprojx b/examples/arm-cm/dpp_efm32-slstk3401a/qxk/armclang/dpp-qxk.uvprojx
index 9e3d7559..ab1a6ba3 100644
--- a/examples/arm-cm/dpp_efm32-slstk3401a/qxk/armclang/dpp-qxk.uvprojx
+++ b/examples/arm-cm/dpp_efm32-slstk3401a/qxk/armclang/dpp-qxk.uvprojx
@@ -337,7 +337,7 @@
0
QXK_USE_IRQ_HANDLER=CRYPTO_IRQHandler QXK_USE_IRQ_NUM=25
+ QXK_USE_IRQ_HANDLER=FPUEH_IRQHandler QXK_USE_IRQ_NUM=33
..\..;..\..\..\..\..\include;..\..\..\..\..\ports\arm-cm\qxk\armclang;..\..\..\..\..\3rd_party\CMSIS\Include;..\..\..\..\..\3rd_party\efm32pg1b
diff --git a/examples/arm-cm/dpp_efm32-slstk3401a/qxk/gnu/Makefile b/examples/arm-cm/dpp_efm32-slstk3401a/qxk/gnu/Makefile
index 2eb10b14..5785e562 100644
--- a/examples/arm-cm/dpp_efm32-slstk3401a/qxk/gnu/Makefile
+++ b/examples/arm-cm/dpp_efm32-slstk3401a/qxk/gnu/Makefile
@@ -1,7 +1,7 @@
##############################################################################
# Product: Makefile for QP/C++ on EMF32-SLSTK3401A, QXK kernel, GNU-ARM
-# Last Updated for Version: 7.2.0
-# Date of the Last Update: 2022-12-14
+# Last Updated for Version: 7.2.1
+# Date of the Last Update: 2023-01-14
#
# Q u a n t u m L e a P s
# ------------------------
@@ -130,8 +130,7 @@ QP_SRCS := \
qxk_xthr.cpp \
qxk_port.cpp
-QP_ASMS := \
-
+QP_ASMS :=
QS_SRCS := \
qs.cpp \
@@ -143,9 +142,9 @@ LIBS :=
# defines
DEFINES := -DEFM32PG1B200F256GM48=1 \
- -DQXK_USE_IRQ_HANDLER=CRYPTO_IRQHandler \
- -DQXK_USE_IRQ_NUM=25 \
- -DQF_ON_CONTEXT_SW
+ -DQF_ON_CONTEXT_SW \
+ -DQK_USE_IRQ_NUM=33 \
+ -DQK_USE_IRQ_HANDLER=FPUEH_IRQHandler
# ARM CPU, ARCH, FPU, and Float-ABI types...
# ARM_CPU: [cortex-m0 | cortex-m0plus | cortex-m1 | cortex-m3 | cortex-m4]
diff --git a/examples/arm-cm/dpp_efm32-slstk3401a/qxk/gnu/Makefile-cpp20 b/examples/arm-cm/dpp_efm32-slstk3401a/qxk/gnu/Makefile-cpp20
index 10c0d701..fd8aa201 100644
--- a/examples/arm-cm/dpp_efm32-slstk3401a/qxk/gnu/Makefile-cpp20
+++ b/examples/arm-cm/dpp_efm32-slstk3401a/qxk/gnu/Makefile-cpp20
@@ -1,13 +1,13 @@
##############################################################################
# Product: Makefile for QP/C++ on EMF32-SLSTK3401A, QXK kernel, GNU-ARM
-# Last Updated for Version: 7.2.0
-# Date of the Last Update: 2022-12-14
+# Last Updated for Version: 7.2.1
+# Date of the Last Update: 2023-01-14
#
# Q u a n t u m L e a P s
# ------------------------
# Modern Embedded Software
#
-# Copyright (C) 2005-2022 Quantum Leaps, LLC. All rights reserved.
+# Copyright (C) 2005 Quantum Leaps, LLC. All rights reserved.
#
# This program is open source software: you can redistribute it and/or
# modify it under the terms of the GNU General Public License as published
@@ -130,8 +130,7 @@ QP_SRCS := \
qxk_xthr.cpp \
qxk_port.cpp
-QP_ASMS := \
-
+QP_ASMS :=
QS_SRCS := \
qs.cpp \
@@ -144,8 +143,8 @@ LIBS :=
# defines
DEFINES := -DEFM32PG1B200F256GM48=1 \
-DQF_ON_CONTEXT_SW \
- -DQXK_USE_IRQ_HANDLER=CRYPTO_IRQHandler \
- -DQXK_USE_IRQ_NUM=25
+ -DQK_USE_IRQ_NUM=33 \
+ -DQK_USE_IRQ_HANDLER=FPUEH_IRQHandler
# ARM CPU, ARCH, FPU, and Float-ABI types...
# ARM_CPU: [cortex-m0 | cortex-m0plus | cortex-m1 | cortex-m3 | cortex-m4]
@@ -186,7 +185,7 @@ MKDIR := mkdir
RM := rm
#-----------------------------------------------------------------------------
-# build options for various configurations for ARM Cortex-M4F
+# build options for various configurations for ARM Cortex-M
#
# combine all the soruces...
diff --git a/examples/arm-cm/dpp_efm32-slstk3401a/qxk/gnu/Makefile-nassert b/examples/arm-cm/dpp_efm32-slstk3401a/qxk/gnu/Makefile-nassert
index c2e8a11b..0ed60e4e 100644
--- a/examples/arm-cm/dpp_efm32-slstk3401a/qxk/gnu/Makefile-nassert
+++ b/examples/arm-cm/dpp_efm32-slstk3401a/qxk/gnu/Makefile-nassert
@@ -1,13 +1,13 @@
##############################################################################
# Product: Makefile for QP/C++ on EMF32-SLSTK3401A, QXK kernel, GNU-ARM
-# Last Updated for Version: 7.2.0
-# Date of the Last Update: 2022-12-14
+# Last Updated for Version: 7.2.1
+# Date of the Last Update: 2023-01-14
#
# Q u a n t u m L e a P s
# ------------------------
# Modern Embedded Software
#
-# Copyright (C) 2005-2022 Quantum Leaps, LLC. All rights reserved.
+# Copyright (C) 2005 Quantum Leaps, LLC. All rights reserved.
#
# This program is open source software: you can redistribute it and/or
# modify it under the terms of the GNU General Public License as published
@@ -130,8 +130,7 @@ QP_SRCS := \
qxk_xthr.cpp \
qxk_port.cpp
-QP_ASMS := \
-
+QP_ASMS :=
QS_SRCS := \
qs.cpp \
@@ -144,9 +143,9 @@ LIBS :=
# defines
DEFINES := -DEFM32PG1B200F256GM48=1 \
-DQF_ON_CONTEXT_SW \
- -DQXK_USE_IRQ_HANDLER=CRYPTO_IRQHandler \
- -DQXK_USE_IRQ_NUM=25 \
- -DQ_NASSERT
+ -DQ_NASSERT \
+ -DQK_USE_IRQ_NUM=33 \
+ -DQK_USE_IRQ_HANDLER=FPUEH_IRQHandler
# ARM CPU, ARCH, FPU, and Float-ABI types...
# ARM_CPU: [cortex-m0 | cortex-m0plus | cortex-m1 | cortex-m3 | cortex-m4]
@@ -187,7 +186,7 @@ MKDIR := mkdir
RM := rm
#-----------------------------------------------------------------------------
-# build options for various configurations for ARM Cortex-M4F
+# build options for various configurations for ARM Cortex-M
#
# combine all the soruces...
diff --git a/examples/arm-cm/dpp_efm32-slstk3401a/qxk/iar/dpp-qxk.ewp b/examples/arm-cm/dpp_efm32-slstk3401a/qxk/iar/dpp-qxk.ewp
index a5608045..2452bd6b 100644
--- a/examples/arm-cm/dpp_efm32-slstk3401a/qxk/iar/dpp-qxk.ewp
+++ b/examples/arm-cm/dpp_efm32-slstk3401a/qxk/iar/dpp-qxk.ewp
@@ -215,8 +215,8 @@
CCDefines
EFM32PG1B200F256GM48
- QXK_USE_IRQ_HANDLER=CRYPTO_IRQHandler
- QXK_USE_IRQ_NUM=25
+ QXK_USE_IRQ_HANDLER=FPUEH_IRQHandler
+ QXK_USE_IRQ_NUM=33
CCPreprocFile
@@ -3264,255 +3264,6 @@
QP_port
$PROJ_DIR$\..\..\..\..\..\ports\arm-cm\qxk\iar\qxk_port.cpp
-
- Debug
-
- ICCARM
-
- 37
- 0
- 1
-
- CCOptimizationNoSizeConstraints
- 0
-
-
- CCDefines
- EFM32PG1B200F256GM48
- QXK_USE_IRQ_NUM=25
- QXK_USE_IRQ_HANDLER=CRYPTO_IRQHandler
-
-
- CCPreprocFile
- 0
-
-
- CCPreprocComments
- 0
-
-
- CCPreprocLine
- 0
-
-
- CCListCFile
- 0
-
-
- CCListCMnemonics
- 0
-
-
- CCListCMessages
- 0
-
-
- CCListAssFile
- 0
-
-
- CCListAssSource
- 0
-
-
- CCEnableRemarks
- 0
-
-
- CCDiagSuppress
- Pe540
-
-
- CCDiagRemark
-
-
- CCDiagWarning
-
-
- CCDiagError
-
-
- CCObjPrefix
- 1
-
-
- CCAllowList
- 1
- 00000000
-
-
- CCDebugInfo
- 1
-
-
- IEndianMode
- 1
-
-
- IProcessor
- 1
-
-
- IExtraOptionsCheck
- 1
-
-
- IExtraOptions
- --enable_restrict
-
-
- CCLangConformance
- 0
-
-
- CCSignedPlainChar
- 1
-
-
- CCRequirePrototypes
- 1
-
-
- CCDiagWarnAreErr
- 0
-
-
- CCCompilerRuntimeInfo
- 0
-
-
- IFpuProcessor
- 1
-
-
- OutputFile
- $FILE_BNAME$.o
-
-
- CCLibConfigHeader
- 1
-
-
- PreInclude
-
-
- CCIncludePath2
- $PROJ_DIR$\..
- $PROJ_DIR$\..\..
- $PROJ_DIR$\..\..\..\..\..\include
- $PROJ_DIR$\..\..\..\..\..\ports\arm-cm\qxk\iar
- $PROJ_DIR$\..\..\..\..\..\3rd_party\CMSIS\Include
- $PROJ_DIR$\..\..\..\..\..\3rd_party\efm32pg1b
-
-
- CCStdIncCheck
- 0
-
-
- CCCodeSection
- .text
-
-
- IProcessorMode2
- 1
-
-
- CCOptLevel
- 1
-
-
- CCOptStrategy
- 0
- 1
-
-
- CCOptLevelSlave
- 1
-
-
- CCPosIndRopi
- 0
-
-
- CCPosIndRwpi
- 0
-
-
- CCPosIndNoDynInit
- 0
-
-
- IccLang
- 2
-
-
- IccCDialect
- 1
-
-
- IccAllowVLA
- 0
-
-
- IccStaticDestr
- 1
-
-
- IccCppInlineSemantics
- 1
-
-
- IccCmsis
- 1
-
-
- IccFloatSemantics
- 0
-
-
- CCNoLiteralPool
- 0
-
-
- CCOptStrategySlave
- 0
- 1
-
-
- CCEncSource
- 0
-
-
- CCEncOutput
- 0
-
-
- CCEncOutputBom
- 1
-
-
- CCEncInput
- 0
-
-
- IccExceptions2
- 0
-
-
- IccRTTI2
- 0
-
-
- CCStackProtection
- 0
-
-
-
-
diff --git a/ports/arm-cm/qk/armclang/qk_port.cpp b/ports/arm-cm/qk/armclang/qk_port.cpp
index 12c49e1a..def2e317 100644
--- a/ports/arm-cm/qk/armclang/qk_port.cpp
+++ b/ports/arm-cm/qk/armclang/qk_port.cpp
@@ -23,8 +23,8 @@
*
============================================================================*/
/*!
-* @date Last updated on: 2022-12-18
-* @version Last updated for: @ref qpc_7_2_0
+* @date Last updated on: 2023-01-14
+* @version Last updated for: @ref qpc_7_2_1
*
* @file
* @brief QK/C++ port to ARM Cortex-M, ARM-CLANG toolset
@@ -104,12 +104,12 @@ void QK_init(void) {
* to return to thread mode (default is to use the NMI exception)
*/
NVIC_IP[QK_USE_IRQ_NUM] = 0U; /* priority 0 (highest) */
- NVIC_EN[QK_USE_IRQ_NUM / 32U] = (1U << (QK_USE_IRQ_NUM % 32U));
+ NVIC_EN[QK_USE_IRQ_NUM >> 5U] = (1U << (QK_USE_IRQ_NUM & 0x1FU));
#endif /*--------- QK IRQ specified */
#if (__ARM_FP != 0) /*--------- if VFP available... */
- /* configure the FPU for QK */
- FPU_FPCCR |= (1U << 30U) /* automatic FPU state preservation (ASPEN) */
+ /* configure the FPU for QK: automatic FPU state preservation (ASPEN) */
+ FPU_FPCCR = FPU_FPCCR | (1U << 30U)
| (1U << 31U); /* lazy stacking (LSPEN) */
#endif /*--------- VFP available */
}
@@ -152,7 +152,7 @@ __asm volatile (
" PUSH {r0,lr} \n" /* ... push lr plus stack-aligner */
#endif /*--------- VFP available */
" MOVS r0,#" STRINGIFY(QF_BASEPRI) "\n"
- " CPSID i \n" /* disable interrutps with BASEPRI */
+ " CPSID i \n" /* disable interrupts with BASEPRI */
" MSR BASEPRI,r0 \n" /* apply the Cortex-M7 erraturm */
" CPSIE i \n" /* 837070, see SDEN-1068427. */
#endif /*--------- ARMv7-M and higher */
@@ -225,9 +225,9 @@ __asm volatile (
" STR r1,[r0] \n" /* ICSR[31] := 1 (pend NMI) */
#else /*--------- use the selected IRQ */
- " LDR r0,=" STRINGIFY(NVIC_PEND + (QK_USE_IRQ_NUM / 32)) "\n"
+ " LDR r0,=" STRINGIFY(NVIC_PEND + ((QK_USE_IRQ_NUM >> 5) << 2)) "\n"
" MOVS r1,#1 \n"
- " LSLS r1,r1,#" STRINGIFY(QK_USE_IRQ_NUM % 32) "\n" /* r1 := IRQ bit */
+ " LSLS r1,r1,#" STRINGIFY(QK_USE_IRQ_NUM & 0x1F) "\n" /* r1 := IRQ bit */
" STR r1,[r0] \n" /* pend the IRQ */
/* now enable interrupts so that pended IRQ can be entered */
diff --git a/ports/arm-cm/qk/gnu/qk_port.cpp b/ports/arm-cm/qk/gnu/qk_port.cpp
index 6688993d..a9b6481a 100644
--- a/ports/arm-cm/qk/gnu/qk_port.cpp
+++ b/ports/arm-cm/qk/gnu/qk_port.cpp
@@ -23,8 +23,8 @@
*
============================================================================*/
/*!
-* @date Last updated on: 2022-12-18
-* @version Last updated for: @ref qpc_7_2_0
+* @date Last updated on: 2023-01-14
+* @version Last updated for: @ref qpc_7_2_1
*
* @file
* @brief QK/C++ port to ARM Cortex-M, GNU-ARM toolset
@@ -72,6 +72,7 @@ void NMI_Handler(void);
* changed by the application-level code.
*/
void QK_init(void) {
+
#if (__ARM_ARCH != 6) /*--------- if ARMv7-M and higher... */
/* set exception priorities to QF_BASEPRI...
@@ -103,12 +104,12 @@ void QK_init(void) {
* to return to thread mode (default is to use the NMI exception)
*/
NVIC_IP[QK_USE_IRQ_NUM] = 0U; /* priority 0 (highest) */
- NVIC_EN[QK_USE_IRQ_NUM / 32U] = (1U << (QK_USE_IRQ_NUM % 32U));
+ NVIC_EN[QK_USE_IRQ_NUM >> 5U] = (1U << (QK_USE_IRQ_NUM & 0x1FU));
#endif /*--------- QK IRQ specified */
#if (__ARM_FP != 0) /*--------- if VFP available... */
- /* configure the FPU for QK */
- FPU_FPCCR |= (1U << 30U) /* automatic FPU state preservation (ASPEN) */
+ /* configure the FPU for QK: automatic FPU state preservation (ASPEN) */
+ FPU_FPCCR = FPU_FPCCR | (1U << 30U)
| (1U << 31U); /* lazy stacking (LSPEN) */
#endif /*--------- VFP available */
}
@@ -156,7 +157,7 @@ __asm volatile (
" PUSH {r0,lr} \n" /* ... push lr plus stack-aligner */
#endif /*--------- VFP available */
" MOV r0,#" STRINGIFY(QF_BASEPRI) "\n"
- " CPSID i \n" /* disable interrutps with BASEPRI */
+ " CPSID i \n" /* disable interrupts with BASEPRI */
" MSR BASEPRI,r0 \n" /* apply the Cortex-M7 erraturm */
" CPSIE i \n" /* 837070, see SDEN-1068427. */
#endif /*--------- ARMv7-M and higher */
@@ -229,9 +230,9 @@ __asm volatile (
" STR r1,[r0] \n" /* ICSR[31] := 1 (pend NMI) */
#else /*--------- use the selected IRQ */
- " LDR r0,=" STRINGIFY(NVIC_PEND + (QK_USE_IRQ_NUM / 32)) "\n"
+ " LDR r0,=" STRINGIFY(NVIC_PEND + ((QK_USE_IRQ_NUM >> 5) << 2)) "\n"
" MOV r1,#1 \n"
- " LSL r1,r1,#" STRINGIFY(QK_USE_IRQ_NUM % 32) "\n" /* r1 := IRQ bit */
+ " LSL r1,r1,#" STRINGIFY(QK_USE_IRQ_NUM & 0x1F) "\n" /* r1 := IRQ bit */
" STR r1,[r0] \n" /* pend the IRQ */
/* now enable interrupts so that pended IRQ can be entered */
@@ -278,7 +279,7 @@ __asm volatile (
" ADD sp,sp,#(8*4) \n" /* remove one 8-register exception frame */
#if (__ARM_FP != 0) /*--------- if VFP available... */
- " POP {r0,lr} \n" /* restore alighner and EXC_RETURN into lr */
+ " POP {r0,lr} \n" /* pop stack aligner and EXC_RETURN to LR */
" DSB \n" /* ARM Erratum 838869 */
#endif /*--------- VFP available */
" BX lr \n" /* return to the preempted task */
diff --git a/ports/arm-cm/qk/iar/qk_port.cpp b/ports/arm-cm/qk/iar/qk_port.cpp
index 4e4a0af5..b25da833 100644
--- a/ports/arm-cm/qk/iar/qk_port.cpp
+++ b/ports/arm-cm/qk/iar/qk_port.cpp
@@ -23,8 +23,8 @@
*
============================================================================*/
/*!
-* @date Last updated on: 2022-12-18
-* @version Last updated for: @ref qpc_7_2_0
+* @date Last updated on: 2023-01-14
+* @version Last updated for: @ref qpc_7_2_1
*
* @file
* @brief QK/C++ port to ARM Cortex-M, IAR-ARM toolset
@@ -72,6 +72,7 @@ void NMI_Handler(void);
* changed by the application-level code.
*/
void QK_init(void) {
+
#if (__ARM_ARCH != 6) /*--------- if ARMv7-M and higher... */
/* set exception priorities to QF_BASEPRI...
@@ -103,12 +104,12 @@ void QK_init(void) {
* to return to thread mode (default is to use the NMI exception)
*/
NVIC_IP[QK_USE_IRQ_NUM] = 0U; /* priority 0 (highest) */
- NVIC_EN[QK_USE_IRQ_NUM / 32U] = (1U << (QK_USE_IRQ_NUM % 32U));
+ NVIC_EN[QK_USE_IRQ_NUM >> 5U] = (1U << (QK_USE_IRQ_NUM & 0x1FU));
#endif /*--------- QK IRQ specified */
#if (__ARM_FP != 0) /*--------- if VFP available... */
- /* configure the FPU for QK */
- FPU_FPCCR |= (1U << 30U) /* automatic FPU state preservation (ASPEN) */
+ /* configure the FPU for QK: automatic FPU state preservation (ASPEN) */
+ FPU_FPCCR = FPU_FPCCR | (1U << 30U)
| (1U << 31U); /* lazy stacking (LSPEN) */
#endif /*--------- VFP available */
}
@@ -151,7 +152,7 @@ __asm volatile (
" PUSH {r0,lr} \n" /* ... push lr plus stack-aligner */
#endif /*--------- VFP available */
" MOVS r0,#" STRINGIFY(QF_BASEPRI) "\n"
- " CPSID i \n" /* disable interrutps with BASEPRI */
+ " CPSID i \n" /* disable interrupts with BASEPRI */
" MSR BASEPRI,r0 \n" /* apply the Cortex-M7 erraturm */
" CPSIE i \n" /* 837070, see SDEN-1068427. */
#endif /*--------- ARMv7-M and higher */
@@ -224,13 +225,9 @@ __asm volatile (
" STR r1,[r0] \n" /* ICSR[31] := 1 (pend NMI) */
#else /*--------- use the selected IRQ */
- " LDR r0,=" STRINGIFY(NVIC_PEND + (QK_USE_IRQ_NUM / 32)) "\n"
+ " LDR r0,=" STRINGIFY(NVIC_PEND + ((QK_USE_IRQ_NUM >> 5) << 2)) "\n"
" MOVS r1,#1 \n"
- /* NOTE: the following IRQ bit calculation should be done simply as
- * (QK_USE_IRQ_NUM % 32), but the IAR assembler does not accept it.
- * As a workaround the modulo (%) operation is replaced with the following:
- */
- " LSLS r1,r1,#" STRINGIFY(QK_USE_IRQ_NUM - (QK_USE_IRQ_NUM/32)*32) "\n"
+ " LSLS r1,r1,#" STRINGIFY(QK_USE_IRQ_NUM & 0x1F) "\n" /* r1 := IRQ bit */
" STR r1,[r0] \n" /* pend the IRQ */
/* now enable interrupts so that pended IRQ can be entered */
diff --git a/ports/arm-cm/qv/armclang/qv_port.cpp b/ports/arm-cm/qv/armclang/qv_port.cpp
index acc785ac..68ea7432 100644
--- a/ports/arm-cm/qv/armclang/qv_port.cpp
+++ b/ports/arm-cm/qv/armclang/qv_port.cpp
@@ -86,8 +86,8 @@ void QV_init(void) {
SCB_SYSPRI[3] = (SCB_SYSPRI[3] | (0xFFU << 16U));
#if (__ARM_FP != 0) /*--------- if VFP available... */
- /* configure the FPU for QK */
- FPU_FPCCR |= (1U << 30U) /* automatic FPU state preservation (ASPEN) */
+ /* configure the FPU for QV: automatic FPU state preservation (ASPEN) */
+ FPU_FPCCR = FPU_FPCCR | (1U << 30U)
| (1U << 31U); /* lazy stacking (LSPEN) */
#endif /*--------- VFP available */
}
diff --git a/ports/arm-cm/qv/gnu/qv_port.cpp b/ports/arm-cm/qv/gnu/qv_port.cpp
index 0a60c1d0..2977ed6c 100644
--- a/ports/arm-cm/qv/gnu/qv_port.cpp
+++ b/ports/arm-cm/qv/gnu/qv_port.cpp
@@ -29,7 +29,7 @@
* @file
* @brief QV/C++ port to ARM Cortex-M, GNU-ARM toolset
*/
-/* This QV port is part of the interanl QP implementation */
+/* This QV port is part of the internal QP implementation */
#define QP_IMPL 1U
#include "qf_port.hpp"
@@ -41,7 +41,8 @@ extern "C" {
#define FPU_FPCCR *((uint32_t volatile *)0xE000EF34U)
/*..........................................................................*/
-/* Initialize the exception priorities and IRQ priorities to safe values.
+/*
+* Initialize the exception priorities and IRQ priorities to safe values.
*
* Description:
* On ARMv7-M or higher, this QK port disables interrupts by means of the
@@ -85,8 +86,8 @@ void QV_init(void) {
SCB_SYSPRI[3] = (SCB_SYSPRI[3] | (0xFFU << 16U));
#if (__ARM_FP != 0) /*--------- if VFP available... */
- /* configure the FPU for QK */
- FPU_FPCCR |= (1U << 30U) /* automatic FPU state preservation (ASPEN) */
+ /* configure the FPU for QV: automatic FPU state preservation (ASPEN) */
+ FPU_FPCCR = FPU_FPCCR | (1U << 30U)
| (1U << 31U); /* lazy stacking (LSPEN) */
#endif /*--------- VFP available */
}
diff --git a/ports/arm-cm/qv/iar/qv_port.cpp b/ports/arm-cm/qv/iar/qv_port.cpp
index bf24e162..c7c78910 100644
--- a/ports/arm-cm/qv/iar/qv_port.cpp
+++ b/ports/arm-cm/qv/iar/qv_port.cpp
@@ -41,7 +41,8 @@ extern "C" {
#define FPU_FPCCR *((uint32_t volatile *)0xE000EF34U)
/*..........................................................................*/
-/* Initialize the exception priorities and IRQ priorities to safe values.
+/*
+* Initialize the exception priorities and IRQ priorities to safe values.
*
* Description:
* On ARMv7-M or higher, this QK port disables interrupts by means of the
@@ -85,8 +86,8 @@ void QV_init(void) {
SCB_SYSPRI[3] = (SCB_SYSPRI[3] | (0xFFU << 16U));
#if (__ARM_FP != 0) /*--------- if VFP available... */
- /* configure the FPU for QK */
- FPU_FPCCR |= (1U << 30U) /* automatic FPU state preservation (ASPEN) */
+ /* configure the FPU for QV: automatic FPU state preservation (ASPEN) */
+ FPU_FPCCR = FPU_FPCCR | (1U << 30U)
| (1U << 31U); /* lazy stacking (LSPEN) */
#endif /*--------- VFP available */
}
diff --git a/ports/arm-cm/qxk/armclang/qxk_port.cpp b/ports/arm-cm/qxk/armclang/qxk_port.cpp
index ad460227..a1fb6480 100644
--- a/ports/arm-cm/qxk/armclang/qxk_port.cpp
+++ b/ports/arm-cm/qxk/armclang/qxk_port.cpp
@@ -1,5 +1,5 @@
/*============================================================================
-* QXK/C++ Real-Time to ARM Cortex-M, ARM-CLANG
+* QP/C++ Real-Time Embedded Framework (RTEF)
* Copyright (C) 2005 Quantum Leaps, LLC. All rights reserved.
*
* SPDX-License-Identifier: GPL-3.0-or-later OR LicenseRef-QL-commercial
@@ -23,8 +23,8 @@
*
============================================================================*/
/*!
-* @date Last updated on: 2022-12-18
-* @version Last updated for: @ref qpc_7_2_0
+* @date Last updated on: 2023-01-14
+* @version Last updated for: @ref qpc_7_2_1
*
* @file
* @brief QXK/C++ port to ARM Cortex-M, ARM-CLANG toolset
@@ -47,11 +47,11 @@ void QXK_USE_IRQ_HANDLER(void);
void NMI_Handler(void);
#endif
-#define SCnSCB_ICTR ((uint32_t volatile *)0xE000E004)
-#define SCB_SYSPRI ((uint32_t volatile *)0xE000ED14)
-#define NVIC_EN ((uint32_t volatile *)0xE000E100)
-#define NVIC_IP ((uint8_t volatile *)0xE000E400)
-#define FPU_FPCCR *((uint32_t volatile *)0xE000EF34)
+#define SCnSCB_ICTR ((uint32_t volatile *)0xE000E004U)
+#define SCB_SYSPRI ((uint32_t volatile *)0xE000ED14U)
+#define NVIC_EN ((uint32_t volatile *)0xE000E100U)
+#define NVIC_IP ((uint8_t volatile *)0xE000E400U)
+#define FPU_FPCCR *((uint32_t volatile *)0xE000EF34U)
#define NVIC_PEND 0xE000E200
#define NVIC_ICSR 0xE000ED04
@@ -104,12 +104,12 @@ void QXK_init(void) {
* to return to thread mode (default is to use the NMI exception)
*/
NVIC_IP[QXK_USE_IRQ_NUM] = 0U; /* priority 0 (highest) */
- NVIC_EN[QXK_USE_IRQ_NUM / 32U] = (1U << (QXK_USE_IRQ_NUM % 32U));
+ NVIC_EN[QXK_USE_IRQ_NUM >> 5U] = (1U << (QXK_USE_IRQ_NUM & 0x1FU));
#endif /*--------- QXK IRQ specified */
#if (__ARM_FP != 0) /*--------- if VFP available... */
- /* configure the FPU for QK */
- FPU_FPCCR |= (1U << 30U) /* automatic FPU state preservation (ASPEN) */
+ /* configure the FPU for QXK: automatic FPU state preservation (ASPEN) */
+ FPU_FPCCR = FPU_FPCCR | (1U << 30U)
| (1U << 31U); /* lazy stacking (LSPEN) */
#endif /*--------- VFP available */
}
@@ -541,9 +541,9 @@ __asm volatile (
" STR r1,[r0] \n" /* ICSR[31] := 1 (pend NMI) */
#else /*--------- use the selected IRQ */
- " LDR r0,=" STRINGIFY(NVIC_PEND + (QXK_USE_IRQ_NUM / 32)) "\n"
+ " LDR r0,=" STRINGIFY(NVIC_PEND + ((QXK_USE_IRQ_NUM >> 5) << 2)) "\n"
" MOVS r1,#1 \n"
- " LSLS r1,r1,#" STRINGIFY(QXK_USE_IRQ_NUM % 32) "\n" /* r1 := IRQ bit */
+ " LSLS r1,r1,#" STRINGIFY(QXK_USE_IRQ_NUM & 0x1F) "\n" /* r1 := IRQ bit */
" STR r1,[r0] \n" /* pend the IRQ */
/* now enable interrupts so that pended IRQ can be entered */
diff --git a/ports/arm-cm/qxk/gnu/qxk_port.cpp b/ports/arm-cm/qxk/gnu/qxk_port.cpp
index 707b1cc3..4d9b9752 100644
--- a/ports/arm-cm/qxk/gnu/qxk_port.cpp
+++ b/ports/arm-cm/qxk/gnu/qxk_port.cpp
@@ -1,5 +1,5 @@
/*============================================================================
-* QP/C Real-Time Embedded Framework (RTEF)
+* QP/C++ Real-Time Embedded Framework (RTEF)
* Copyright (C) 2005 Quantum Leaps, LLC. All rights reserved.
*
* SPDX-License-Identifier: GPL-3.0-or-later OR LicenseRef-QL-commercial
@@ -23,8 +23,8 @@
*
============================================================================*/
/*!
-* @date Last updated on: 2022-12-18
-* @version Last updated for: @ref qpc_7_2_0
+* @date Last updated on: 2023-01-14
+* @version Last updated for: @ref qpc_7_2_1
*
* @file
* @brief QXK/C++ port to ARM Cortex-M, GNU-ARM toolset
@@ -104,12 +104,12 @@ void QXK_init(void) {
* to return to thread mode (default is to use the NMI exception)
*/
NVIC_IP[QXK_USE_IRQ_NUM] = 0U; /* priority 0 (highest) */
- NVIC_EN[QXK_USE_IRQ_NUM / 32U] = (1U << (QXK_USE_IRQ_NUM % 32U));
+ NVIC_EN[QXK_USE_IRQ_NUM >> 5U] = (1U << (QXK_USE_IRQ_NUM & 0x1FU));
#endif /*--------- QXK IRQ specified */
#if (__ARM_FP != 0) /*--------- if VFP available... */
- /* configure the FPU for QK */
- FPU_FPCCR |= (1U << 30U) /* automatic FPU state preservation (ASPEN) */
+ /* configure the FPU for QXK: automatic FPU state preservation (ASPEN) */
+ FPU_FPCCR = FPU_FPCCR | (1U << 30U)
| (1U << 31U); /* lazy stacking (LSPEN) */
#endif /*--------- VFP available */
}
@@ -546,9 +546,9 @@ __asm volatile (
" STR r1,[r0] \n" /* ICSR[31] := 1 (pend NMI) */
#else /*--------- use the selected IRQ */
- " LDR r0,=" STRINGIFY(NVIC_PEND + (QXK_USE_IRQ_NUM / 32)) "\n"
+ " LDR r0,=" STRINGIFY(NVIC_PEND + ((QXK_USE_IRQ_NUM >> 5) << 2)) "\n"
" MOV r1,#1 \n"
- " LSL r1,r1,#" STRINGIFY(QXK_USE_IRQ_NUM % 32) "\n" /* r1 := IRQ bit */
+ " LSL r1,r1,#" STRINGIFY(QXK_USE_IRQ_NUM & 0x1F) "\n" /* r1 := IRQ bit */
" STR r1,[r0] \n" /* pend the IRQ */
/* now enable interrupts so that pended IRQ can be entered */
diff --git a/ports/arm-cm/qxk/iar/qxk_port.cpp b/ports/arm-cm/qxk/iar/qxk_port.cpp
index 73dec1ec..bf8f5614 100644
--- a/ports/arm-cm/qxk/iar/qxk_port.cpp
+++ b/ports/arm-cm/qxk/iar/qxk_port.cpp
@@ -1,5 +1,5 @@
/*============================================================================
-* QP/C Real-Time Embedded Framework (RTEF)
+* QP/C++ Real-Time Embedded Framework (RTEF)
* Copyright (C) 2005 Quantum Leaps, LLC. All rights reserved.
*
* SPDX-License-Identifier: GPL-3.0-or-later OR LicenseRef-QL-commercial
@@ -23,8 +23,8 @@
*
============================================================================*/
/*!
-* @date Last updated on: 2022-12-18
-* @version Last updated for: @ref qpc_7_2_0
+* @date Last updated on: 2023-01-14
+* @version Last updated for: @ref qpc_7_2_1
*
* @file
* @brief QXK/C++ port to ARM Cortex-M, IAR-ARM toolset
@@ -104,12 +104,12 @@ void QXK_init(void) {
* to return to thread mode (default is to use the NMI exception)
*/
NVIC_IP[QXK_USE_IRQ_NUM] = 0U; /* priority 0 (highest) */
- NVIC_EN[QXK_USE_IRQ_NUM / 32U] = (1U << (QXK_USE_IRQ_NUM % 32U));
+ NVIC_EN[QXK_USE_IRQ_NUM >> 5U] = (1U << (QXK_USE_IRQ_NUM & 0x1FU));
#endif /*--------- QXK IRQ specified */
#if (__ARM_FP != 0) /*--------- if VFP available... */
- /* configure the FPU for QK */
- FPU_FPCCR |= (1U << 30U) /* automatic FPU state preservation (ASPEN) */
+ /* configure the FPU for QXK: automatic FPU state preservation (ASPEN) */
+ FPU_FPCCR = FPU_FPCCR | (1U << 30U)
| (1U << 31U); /* lazy stacking (LSPEN) */
#endif /*--------- VFP available */
}
@@ -541,13 +541,9 @@ __asm volatile (
" STR r1,[r0] \n" /* ICSR[31] := 1 (pend NMI) */
#else /*--------- use the selected IRQ */
- " LDR r0,=" STRINGIFY(NVIC_PEND + (QXK_USE_IRQ_NUM / 32)) "\n"
+ " LDR r0,=" STRINGIFY(NVIC_PEND + ((QXK_USE_IRQ_NUM >> 5) << 2)) "\n"
" MOVS r1,#1 \n"
- /* NOTE: the following IRQ bit calculation should be done simply as
- * (QXK_USE_IRQ_NUM % 32), but the IAR assembler does not accept it.
- * As a workaround the modulo (%) operation is replaced with the following:
- */
- " LSLS r1,r1,#" STRINGIFY(QXK_USE_IRQ_NUM - (QXK_USE_IRQ_NUM/32)*32) "\n"
+ " LSLS r1,r1,#" STRINGIFY(QXK_USE_IRQ_NUM & 0x1F) "\n" /* r1 := IRQ bit */
" STR r1,[r0] \n" /* pend the IRQ */
/* now enable interrupts so that pended IRQ can be entered */