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7.2.1

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This commit is contained in:
MMS 2023-01-14 21:11:28 -05:00
parent a3bc0977d5
commit c502b0e716
18 changed files with 106 additions and 612 deletions
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2
examples/arm-cm/dpp_efm32-slstk3401a/qk/armclang/dpp-qk.uvprojx
View File

@ -337,7 +337,7 @@
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define>QK_USE_IRQ_NUM=25 QK_USE_IRQ_HANDLER=CRYPTO_IRQHandler</Define>
<Define>QK_USE_IRQ_NUM=33 QK_USE_IRQ_HANDLER=FPUEH_IRQHandler</Define>
<Undefine></Undefine>
<IncludePath>..\..;..\..\..\..\..\include;..\..\..\..\..\ports\arm-cm\qk\armclang;..\..\..\..\..\3rd_party\CMSIS\Include;..\..\..\..\..\3rd_party\efm32pg1b</IncludePath>
</VariousControls>

14
examples/arm-cm/dpp_efm32-slstk3401a/qk/gnu/Makefile
View File

@ -1,13 +1,13 @@
##############################################################################
# Product: Makefile for QP/C++ on EMF32-SLSTK3401A, QK kernel, GNU-ARM
# Last Updated for Version: 7.0.1
# Date of the Last Update: 2022-05-23
# Last Updated for Version: 7.2.1
# Date of the Last Update: 2023-01-14
#
# Q u a n t u m L e a P s
# ------------------------
# Modern Embedded Software
#
# Copyright (C) 2005-2021 Quantum Leaps, LLC. All rights reserved.
# Copyright (C) 2005 Quantum Leaps, LLC. All rights reserved.
#
# This program is open source software: you can redistribute it and/or
# modify it under the terms of the GNU General Public License as published
@ -45,7 +45,7 @@
# NOTE:
# To use this Makefile on Windows, you will need the GNU make utility, which
# is included in the Qtools collection for Windows, see:
# http://sourceforge.net/projects/qpc/files/Qtools/
# https://github.com/QuantumLeaps/qtools/releases
#
#-----------------------------------------------------------------------------
@ -138,8 +138,8 @@ LIBS :=
# defines
DEFINES := -DEFM32PG1B200F256GM48=1 \
-DQK_USE_IRQ_HANDLER=CRYPTO_IRQHandler \
-DQK_USE_IRQ_NUM=25
-DQK_USE_IRQ_NUM=33 \
-DQK_USE_IRQ_HANDLER=FPUEH_IRQHandler
# ARM CPU, ARCH, FPU, and Float-ABI types...
# ARM_CPU: [cortex-m0 | cortex-m0plus | cortex-m1 | cortex-m3 | cortex-m4]
@ -180,7 +180,7 @@ MKDIR := mkdir
RM := rm
#-----------------------------------------------------------------------------
# build options for various configurations for ARM Cortex-M4F
# build options for various configurations for ARM Cortex-M
#
# combine all the soruces...

11
examples/arm-cm/dpp_efm32-slstk3401a/qk/gnu/Makefile-cpp20
View File

@ -1,13 +1,13 @@
##############################################################################
# Product: Makefile for QP/C++ on EMF32-SLSTK3401A, QK kernel, GNU-ARM
# Last Updated for Version: 7.0.0
# Date of the Last Update: 2022-05-13
# Last Updated for Version: 7.2.1
# Date of the Last Update: 2023-01-14
#
# Q u a n t u m L e a P s
# ------------------------
# Modern Embedded Software
#
# Copyright (C) 2005-2022 Quantum Leaps, LLC. All rights reserved.
# Copyright (C) 2005 Quantum Leaps, LLC. All rights reserved.
#
# This program is open source software: you can redistribute it and/or
# modify it under the terms of the GNU General Public License as published
@ -80,7 +80,6 @@ VPATH = \
INCLUDES = \
-I../.. \
-I$(QPCPP)/include \
-I$(QPCPP)/src \
-I$(QP_PORT_DIR) \
-I$(QPCPP)/3rd_party/CMSIS/Include \
-I$(QPCPP)/3rd_party/efm32pg1b
@ -139,8 +138,8 @@ LIBS :=
# defines
DEFINES := -DEFM32PG1B200F256GM48=1 \
-DQK_USE_IRQ_NUM=25 \
-DQK_USE_IRQ_HANDLER=CRYPTO_IRQHandler
-DQK_USE_IRQ_NUM=33 \
-DQK_USE_IRQ_HANDLER=FPUEH_IRQHandler
# ARM CPU, ARCH, FPU, and Float-ABI types...
# ARM_CPU: [cortex-m0 | cortex-m0plus | cortex-m1 | cortex-m3 | cortex-m4]

253
examples/arm-cm/dpp_efm32-slstk3401a/qk/iar/dpp-qk.ewp
View File

@ -215,8 +215,8 @@
<option>
<name>CCDefines</name>
<state>EFM32PG1B200F256GM48</state>
<state>QK_USE_IRQ_HANDLER=CRYPTO_IRQHandler</state>
<state>QK_USE_IRQ_NUM=25</state>
<state>QK_USE_IRQ_HANDLER=FPUEH_IRQHandler</state>
<state>QK_USE_IRQ_NUM=33</state>
</option>
<option>
<name>CCPreprocFile</name>
@ -3258,255 +3258,6 @@
<name>QP_port</name>
<file>
<name>$PROJ_DIR$\..\..\..\..\..\ports\arm-cm\qk\iar\qk_port.cpp</name>
<configuration>
<name>Debug</name>
<settings>
<name>ICCARM</name>
<data>
<version>37</version>
<wantNonLocal>0</wantNonLocal>
<debug>1</debug>
<option>
<name>CCOptimizationNoSizeConstraints</name>
<state>0</state>
</option>
<option>
<name>CCDefines</name>
<state>EFM32PG1B200F256GM48</state>
<state>QK_USE_IRQ_NUM=25</state>
<state>QK_USE_IRQ_HANDLER=CRYPTO_IRQHandler</state>
</option>
<option>
<name>CCPreprocFile</name>
<state>0</state>
</option>
<option>
<name>CCPreprocComments</name>
<state>0</state>
</option>
<option>
<name>CCPreprocLine</name>
<state>0</state>
</option>
<option>
<name>CCListCFile</name>
<state>0</state>
</option>
<option>
<name>CCListCMnemonics</name>
<state>0</state>
</option>
<option>
<name>CCListCMessages</name>
<state>0</state>
</option>
<option>
<name>CCListAssFile</name>
<state>0</state>
</option>
<option>
<name>CCListAssSource</name>
<state>0</state>
</option>
<option>
<name>CCEnableRemarks</name>
<state>0</state>
</option>
<option>
<name>CCDiagSuppress</name>
<state>Pe540</state>
</option>
<option>
<name>CCDiagRemark</name>
<state></state>
</option>
<option>
<name>CCDiagWarning</name>
<state></state>
</option>
<option>
<name>CCDiagError</name>
<state></state>
</option>
<option>
<name>CCObjPrefix</name>
<state>1</state>
</option>
<option>
<name>CCAllowList</name>
<version>1</version>
<state>00000000</state>
</option>
<option>
<name>CCDebugInfo</name>
<state>1</state>
</option>
<option>
<name>IEndianMode</name>
<state>1</state>
</option>
<option>
<name>IProcessor</name>
<state>1</state>
</option>
<option>
<name>IExtraOptionsCheck</name>
<state>1</state>
</option>
<option>
<name>IExtraOptions</name>
<state>--enable_restrict</state>
</option>
<option>
<name>CCLangConformance</name>
<state>0</state>
</option>
<option>
<name>CCSignedPlainChar</name>
<state>1</state>
</option>
<option>
<name>CCRequirePrototypes</name>
<state>1</state>
</option>
<option>
<name>CCDiagWarnAreErr</name>
<state>0</state>
</option>
<option>
<name>CCCompilerRuntimeInfo</name>
<state>0</state>
</option>
<option>
<name>IFpuProcessor</name>
<state>1</state>
</option>
<option>
<name>OutputFile</name>
<state>$FILE_BNAME$.o</state>
</option>
<option>
<name>CCLibConfigHeader</name>
<state>1</state>
</option>
<option>
<name>PreInclude</name>
<state></state>
</option>
<option>
<name>CCIncludePath2</name>
<state>$PROJ_DIR$\..</state>
<state>$PROJ_DIR$\..\..</state>
<state>$PROJ_DIR$\..\..\..\..\..\include</state>
<state>$PROJ_DIR$\..\..\..\..\..\ports\arm-cm\qk\iar</state>
<state>$PROJ_DIR$\..\..\..\..\..\3rd_party\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\..\3rd_party\efm32pg1b</state>
</option>
<option>
<name>CCStdIncCheck</name>
<state>0</state>
</option>
<option>
<name>CCCodeSection</name>
<state>.text</state>
</option>
<option>
<name>IProcessorMode2</name>
<state>1</state>
</option>
<option>
<name>CCOptLevel</name>
<state>1</state>
</option>
<option>
<name>CCOptStrategy</name>
<version>0</version>
<state>1</state>
</option>
<option>
<name>CCOptLevelSlave</name>
<state>1</state>
</option>
<option>
<name>CCPosIndRopi</name>
<state>0</state>
</option>
<option>
<name>CCPosIndRwpi</name>
<state>0</state>
</option>
<option>
<name>CCPosIndNoDynInit</name>
<state>0</state>
</option>
<option>
<name>IccLang</name>
<state>2</state>
</option>
<option>
<name>IccCDialect</name>
<state>1</state>
</option>
<option>
<name>IccAllowVLA</name>
<state>0</state>
</option>
<option>
<name>IccStaticDestr</name>
<state>1</state>
</option>
<option>
<name>IccCppInlineSemantics</name>
<state>1</state>
</option>
<option>
<name>IccCmsis</name>
<state>1</state>
</option>
<option>
<name>IccFloatSemantics</name>
<state>0</state>
</option>
<option>
<name>CCNoLiteralPool</name>
<state>0</state>
</option>
<option>
<name>CCOptStrategySlave</name>
<version>0</version>
<state>1</state>
</option>
<option>
<name>CCEncSource</name>
<state>0</state>
</option>
<option>
<name>CCEncOutput</name>
<state>0</state>
</option>
<option>
<name>CCEncOutputBom</name>
<state>1</state>
</option>
<option>
<name>CCEncInput</name>
<state>0</state>
</option>
<option>
<name>IccExceptions2</name>
<state>0</state>
</option>
<option>
<name>IccRTTI2</name>
<state>0</state>
</option>
<option>
<name>CCStackProtection</name>
<state>0</state>
</option>
</data>
</settings>
</configuration>
</file>
</group>
<group>

2
examples/arm-cm/dpp_efm32-slstk3401a/qxk/armclang/dpp-qxk.uvprojx
View File

@ -337,7 +337,7 @@
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define>QXK_USE_IRQ_HANDLER=CRYPTO_IRQHandler QXK_USE_IRQ_NUM=25</Define>
<Define>QXK_USE_IRQ_HANDLER=FPUEH_IRQHandler QXK_USE_IRQ_NUM=33</Define>
<Undefine></Undefine>
<IncludePath>..\..;..\..\..\..\..\include;..\..\..\..\..\ports\arm-cm\qxk\armclang;..\..\..\..\..\3rd_party\CMSIS\Include;..\..\..\..\..\3rd_party\efm32pg1b</IncludePath>
</VariousControls>

13
examples/arm-cm/dpp_efm32-slstk3401a/qxk/gnu/Makefile
View File

@ -1,7 +1,7 @@
##############################################################################
# Product: Makefile for QP/C++ on EMF32-SLSTK3401A, QXK kernel, GNU-ARM
# Last Updated for Version: 7.2.0
# Date of the Last Update: 2022-12-14
# Last Updated for Version: 7.2.1
# Date of the Last Update: 2023-01-14
#
# Q u a n t u m L e a P s
# ------------------------
@ -130,8 +130,7 @@ QP_SRCS := \
qxk_xthr.cpp \
qxk_port.cpp
QP_ASMS := \
QP_ASMS :=
QS_SRCS := \
qs.cpp \
@ -143,9 +142,9 @@ LIBS :=
# defines
DEFINES := -DEFM32PG1B200F256GM48=1 \
-DQXK_USE_IRQ_HANDLER=CRYPTO_IRQHandler \
-DQXK_USE_IRQ_NUM=25 \
-DQF_ON_CONTEXT_SW
-DQF_ON_CONTEXT_SW \
-DQK_USE_IRQ_NUM=33 \
-DQK_USE_IRQ_HANDLER=FPUEH_IRQHandler
# ARM CPU, ARCH, FPU, and Float-ABI types...
# ARM_CPU: [cortex-m0 | cortex-m0plus | cortex-m1 | cortex-m3 | cortex-m4]

15
examples/arm-cm/dpp_efm32-slstk3401a/qxk/gnu/Makefile-cpp20
View File

@ -1,13 +1,13 @@
##############################################################################
# Product: Makefile for QP/C++ on EMF32-SLSTK3401A, QXK kernel, GNU-ARM
# Last Updated for Version: 7.2.0
# Date of the Last Update: 2022-12-14
# Last Updated for Version: 7.2.1
# Date of the Last Update: 2023-01-14
#
# Q u a n t u m L e a P s
# ------------------------
# Modern Embedded Software
#
# Copyright (C) 2005-2022 Quantum Leaps, LLC. All rights reserved.
# Copyright (C) 2005 Quantum Leaps, LLC. All rights reserved.
#
# This program is open source software: you can redistribute it and/or
# modify it under the terms of the GNU General Public License as published
@ -130,8 +130,7 @@ QP_SRCS := \
qxk_xthr.cpp \
qxk_port.cpp
QP_ASMS := \
QP_ASMS :=
QS_SRCS := \
qs.cpp \
@ -144,8 +143,8 @@ LIBS :=
# defines
DEFINES := -DEFM32PG1B200F256GM48=1 \
-DQF_ON_CONTEXT_SW \
-DQXK_USE_IRQ_HANDLER=CRYPTO_IRQHandler \
-DQXK_USE_IRQ_NUM=25
-DQK_USE_IRQ_NUM=33 \
-DQK_USE_IRQ_HANDLER=FPUEH_IRQHandler
# ARM CPU, ARCH, FPU, and Float-ABI types...
# ARM_CPU: [cortex-m0 | cortex-m0plus | cortex-m1 | cortex-m3 | cortex-m4]
@ -186,7 +185,7 @@ MKDIR := mkdir
RM := rm
#-----------------------------------------------------------------------------
# build options for various configurations for ARM Cortex-M4F
# build options for various configurations for ARM Cortex-M
#
# combine all the soruces...

17
examples/arm-cm/dpp_efm32-slstk3401a/qxk/gnu/Makefile-nassert
View File

@ -1,13 +1,13 @@
##############################################################################
# Product: Makefile for QP/C++ on EMF32-SLSTK3401A, QXK kernel, GNU-ARM
# Last Updated for Version: 7.2.0
# Date of the Last Update: 2022-12-14
# Last Updated for Version: 7.2.1
# Date of the Last Update: 2023-01-14
#
# Q u a n t u m L e a P s
# ------------------------
# Modern Embedded Software
#
# Copyright (C) 2005-2022 Quantum Leaps, LLC. All rights reserved.
# Copyright (C) 2005 Quantum Leaps, LLC. All rights reserved.
#
# This program is open source software: you can redistribute it and/or
# modify it under the terms of the GNU General Public License as published
@ -130,8 +130,7 @@ QP_SRCS := \
qxk_xthr.cpp \
qxk_port.cpp
QP_ASMS := \
QP_ASMS :=
QS_SRCS := \
qs.cpp \
@ -144,9 +143,9 @@ LIBS :=
# defines
DEFINES := -DEFM32PG1B200F256GM48=1 \
-DQF_ON_CONTEXT_SW \
-DQXK_USE_IRQ_HANDLER=CRYPTO_IRQHandler \
-DQXK_USE_IRQ_NUM=25 \
-DQ_NASSERT
-DQ_NASSERT \
-DQK_USE_IRQ_NUM=33 \
-DQK_USE_IRQ_HANDLER=FPUEH_IRQHandler
# ARM CPU, ARCH, FPU, and Float-ABI types...
# ARM_CPU: [cortex-m0 | cortex-m0plus | cortex-m1 | cortex-m3 | cortex-m4]
@ -187,7 +186,7 @@ MKDIR := mkdir
RM := rm
#-----------------------------------------------------------------------------
# build options for various configurations for ARM Cortex-M4F
# build options for various configurations for ARM Cortex-M
#
# combine all the soruces...

253
examples/arm-cm/dpp_efm32-slstk3401a/qxk/iar/dpp-qxk.ewp
View File

@ -215,8 +215,8 @@
<option>
<name>CCDefines</name>
<state>EFM32PG1B200F256GM48</state>
<state>QXK_USE_IRQ_HANDLER=CRYPTO_IRQHandler</state>
<state>QXK_USE_IRQ_NUM=25</state>
<state>QXK_USE_IRQ_HANDLER=FPUEH_IRQHandler</state>
<state>QXK_USE_IRQ_NUM=33</state>
</option>
<option>
<name>CCPreprocFile</name>
@ -3264,255 +3264,6 @@
<name>QP_port</name>
<file>
<name>$PROJ_DIR$\..\..\..\..\..\ports\arm-cm\qxk\iar\qxk_port.cpp</name>
<configuration>
<name>Debug</name>
<settings>
<name>ICCARM</name>
<data>
<version>37</version>
<wantNonLocal>0</wantNonLocal>
<debug>1</debug>
<option>
<name>CCOptimizationNoSizeConstraints</name>
<state>0</state>
</option>
<option>
<name>CCDefines</name>
<state>EFM32PG1B200F256GM48</state>
<state>QXK_USE_IRQ_NUM=25</state>
<state>QXK_USE_IRQ_HANDLER=CRYPTO_IRQHandler</state>
</option>
<option>
<name>CCPreprocFile</name>
<state>0</state>
</option>
<option>
<name>CCPreprocComments</name>
<state>0</state>
</option>
<option>
<name>CCPreprocLine</name>
<state>0</state>
</option>
<option>
<name>CCListCFile</name>
<state>0</state>
</option>
<option>
<name>CCListCMnemonics</name>
<state>0</state>
</option>
<option>
<name>CCListCMessages</name>
<state>0</state>
</option>
<option>
<name>CCListAssFile</name>
<state>0</state>
</option>
<option>
<name>CCListAssSource</name>
<state>0</state>
</option>
<option>
<name>CCEnableRemarks</name>
<state>0</state>
</option>
<option>
<name>CCDiagSuppress</name>
<state>Pe540</state>
</option>
<option>
<name>CCDiagRemark</name>
<state></state>
</option>
<option>
<name>CCDiagWarning</name>
<state></state>
</option>
<option>
<name>CCDiagError</name>
<state></state>
</option>
<option>
<name>CCObjPrefix</name>
<state>1</state>
</option>
<option>
<name>CCAllowList</name>
<version>1</version>
<state>00000000</state>
</option>
<option>
<name>CCDebugInfo</name>
<state>1</state>
</option>
<option>
<name>IEndianMode</name>
<state>1</state>
</option>
<option>
<name>IProcessor</name>
<state>1</state>
</option>
<option>
<name>IExtraOptionsCheck</name>
<state>1</state>
</option>
<option>
<name>IExtraOptions</name>
<state>--enable_restrict</state>
</option>
<option>
<name>CCLangConformance</name>
<state>0</state>
</option>
<option>
<name>CCSignedPlainChar</name>
<state>1</state>
</option>
<option>
<name>CCRequirePrototypes</name>
<state>1</state>
</option>
<option>
<name>CCDiagWarnAreErr</name>
<state>0</state>
</option>
<option>
<name>CCCompilerRuntimeInfo</name>
<state>0</state>
</option>
<option>
<name>IFpuProcessor</name>
<state>1</state>
</option>
<option>
<name>OutputFile</name>
<state>$FILE_BNAME$.o</state>
</option>
<option>
<name>CCLibConfigHeader</name>
<state>1</state>
</option>
<option>
<name>PreInclude</name>
<state></state>
</option>
<option>
<name>CCIncludePath2</name>
<state>$PROJ_DIR$\..</state>
<state>$PROJ_DIR$\..\..</state>
<state>$PROJ_DIR$\..\..\..\..\..\include</state>
<state>$PROJ_DIR$\..\..\..\..\..\ports\arm-cm\qxk\iar</state>
<state>$PROJ_DIR$\..\..\..\..\..\3rd_party\CMSIS\Include</state>
<state>$PROJ_DIR$\..\..\..\..\..\3rd_party\efm32pg1b</state>
</option>
<option>
<name>CCStdIncCheck</name>
<state>0</state>
</option>
<option>
<name>CCCodeSection</name>
<state>.text</state>
</option>
<option>
<name>IProcessorMode2</name>
<state>1</state>
</option>
<option>
<name>CCOptLevel</name>
<state>1</state>
</option>
<option>
<name>CCOptStrategy</name>
<version>0</version>
<state>1</state>
</option>
<option>
<name>CCOptLevelSlave</name>
<state>1</state>
</option>
<option>
<name>CCPosIndRopi</name>
<state>0</state>
</option>
<option>
<name>CCPosIndRwpi</name>
<state>0</state>
</option>
<option>
<name>CCPosIndNoDynInit</name>
<state>0</state>
</option>
<option>
<name>IccLang</name>
<state>2</state>
</option>
<option>
<name>IccCDialect</name>
<state>1</state>
</option>
<option>
<name>IccAllowVLA</name>
<state>0</state>
</option>
<option>
<name>IccStaticDestr</name>
<state>1</state>
</option>
<option>
<name>IccCppInlineSemantics</name>
<state>1</state>
</option>
<option>
<name>IccCmsis</name>
<state>1</state>
</option>
<option>
<name>IccFloatSemantics</name>
<state>0</state>
</option>
<option>
<name>CCNoLiteralPool</name>
<state>0</state>
</option>
<option>
<name>CCOptStrategySlave</name>
<version>0</version>
<state>1</state>
</option>
<option>
<name>CCEncSource</name>
<state>0</state>
</option>
<option>
<name>CCEncOutput</name>
<state>0</state>
</option>
<option>
<name>CCEncOutputBom</name>
<state>1</state>
</option>
<option>
<name>CCEncInput</name>
<state>0</state>
</option>
<option>
<name>IccExceptions2</name>
<state>0</state>
</option>
<option>
<name>IccRTTI2</name>
<state>0</state>
</option>
<option>
<name>CCStackProtection</name>
<state>0</state>
</option>
</data>
</settings>
</configuration>
</file>
</group>
<group>

16
ports/arm-cm/qk/armclang/qk_port.cpp
View File

@ -23,8 +23,8 @@
* <info@state-machine.com>
============================================================================*/
/*!
* @date Last updated on: 2022-12-18
* @version Last updated for: @ref qpc_7_2_0
* @date Last updated on: 2023-01-14
* @version Last updated for: @ref qpc_7_2_1
*
* @file
* @brief QK/C++ port to ARM Cortex-M, ARM-CLANG toolset
@ -104,12 +104,12 @@ void QK_init(void) {
* to return to thread mode (default is to use the NMI exception)
*/
NVIC_IP[QK_USE_IRQ_NUM] = 0U; /* priority 0 (highest) */
NVIC_EN[QK_USE_IRQ_NUM / 32U] = (1U << (QK_USE_IRQ_NUM % 32U));
NVIC_EN[QK_USE_IRQ_NUM >> 5U] = (1U << (QK_USE_IRQ_NUM & 0x1FU));
#endif /*--------- QK IRQ specified */
#if (__ARM_FP != 0) /*--------- if VFP available... */
/* configure the FPU for QK */
FPU_FPCCR |= (1U << 30U) /* automatic FPU state preservation (ASPEN) */
/* configure the FPU for QK: automatic FPU state preservation (ASPEN) */
FPU_FPCCR = FPU_FPCCR | (1U << 30U)
| (1U << 31U); /* lazy stacking (LSPEN) */
#endif /*--------- VFP available */
}
@ -152,7 +152,7 @@ __asm volatile (
" PUSH {r0,lr} \n" /* ... push lr plus stack-aligner */
#endif /*--------- VFP available */
" MOVS r0,#" STRINGIFY(QF_BASEPRI) "\n"
" CPSID i \n" /* disable interrutps with BASEPRI */
" CPSID i \n" /* disable interrupts with BASEPRI */
" MSR BASEPRI,r0 \n" /* apply the Cortex-M7 erraturm */
" CPSIE i \n" /* 837070, see SDEN-1068427. */
#endif /*--------- ARMv7-M and higher */
@ -225,9 +225,9 @@ __asm volatile (
" STR r1,[r0] \n" /* ICSR[31] := 1 (pend NMI) */
#else /*--------- use the selected IRQ */
" LDR r0,=" STRINGIFY(NVIC_PEND + (QK_USE_IRQ_NUM / 32)) "\n"
" LDR r0,=" STRINGIFY(NVIC_PEND + ((QK_USE_IRQ_NUM >> 5) << 2)) "\n"
" MOVS r1,#1 \n"
" LSLS r1,r1,#" STRINGIFY(QK_USE_IRQ_NUM % 32) "\n" /* r1 := IRQ bit */
" LSLS r1,r1,#" STRINGIFY(QK_USE_IRQ_NUM & 0x1F) "\n" /* r1 := IRQ bit */
" STR r1,[r0] \n" /* pend the IRQ */
/* now enable interrupts so that pended IRQ can be entered */

19
ports/arm-cm/qk/gnu/qk_port.cpp
View File

@ -23,8 +23,8 @@
* <info@state-machine.com>
============================================================================*/
/*!
* @date Last updated on: 2022-12-18
* @version Last updated for: @ref qpc_7_2_0
* @date Last updated on: 2023-01-14
* @version Last updated for: @ref qpc_7_2_1
*
* @file
* @brief QK/C++ port to ARM Cortex-M, GNU-ARM toolset
@ -72,6 +72,7 @@ void NMI_Handler(void);
* changed by the application-level code.
*/
void QK_init(void) {
#if (__ARM_ARCH != 6) /*--------- if ARMv7-M and higher... */
/* set exception priorities to QF_BASEPRI...
@ -103,12 +104,12 @@ void QK_init(void) {
* to return to thread mode (default is to use the NMI exception)
*/
NVIC_IP[QK_USE_IRQ_NUM] = 0U; /* priority 0 (highest) */
NVIC_EN[QK_USE_IRQ_NUM / 32U] = (1U << (QK_USE_IRQ_NUM % 32U));
NVIC_EN[QK_USE_IRQ_NUM >> 5U] = (1U << (QK_USE_IRQ_NUM & 0x1FU));
#endif /*--------- QK IRQ specified */
#if (__ARM_FP != 0) /*--------- if VFP available... */
/* configure the FPU for QK */
FPU_FPCCR |= (1U << 30U) /* automatic FPU state preservation (ASPEN) */
/* configure the FPU for QK: automatic FPU state preservation (ASPEN) */
FPU_FPCCR = FPU_FPCCR | (1U << 30U)
| (1U << 31U); /* lazy stacking (LSPEN) */
#endif /*--------- VFP available */
}
@ -156,7 +157,7 @@ __asm volatile (
" PUSH {r0,lr} \n" /* ... push lr plus stack-aligner */
#endif /*--------- VFP available */
" MOV r0,#" STRINGIFY(QF_BASEPRI) "\n"
" CPSID i \n" /* disable interrutps with BASEPRI */
" CPSID i \n" /* disable interrupts with BASEPRI */
" MSR BASEPRI,r0 \n" /* apply the Cortex-M7 erraturm */
" CPSIE i \n" /* 837070, see SDEN-1068427. */
#endif /*--------- ARMv7-M and higher */
@ -229,9 +230,9 @@ __asm volatile (
" STR r1,[r0] \n" /* ICSR[31] := 1 (pend NMI) */
#else /*--------- use the selected IRQ */
" LDR r0,=" STRINGIFY(NVIC_PEND + (QK_USE_IRQ_NUM / 32)) "\n"
" LDR r0,=" STRINGIFY(NVIC_PEND + ((QK_USE_IRQ_NUM >> 5) << 2)) "\n"
" MOV r1,#1 \n"
" LSL r1,r1,#" STRINGIFY(QK_USE_IRQ_NUM % 32) "\n" /* r1 := IRQ bit */
" LSL r1,r1,#" STRINGIFY(QK_USE_IRQ_NUM & 0x1F) "\n" /* r1 := IRQ bit */
" STR r1,[r0] \n" /* pend the IRQ */
/* now enable interrupts so that pended IRQ can be entered */
@ -278,7 +279,7 @@ __asm volatile (
" ADD sp,sp,#(8*4) \n" /* remove one 8-register exception frame */
#if (__ARM_FP != 0) /*--------- if VFP available... */
" POP {r0,lr} \n" /* restore alighner and EXC_RETURN into lr */
" POP {r0,lr} \n" /* pop stack aligner and EXC_RETURN to LR */
" DSB \n" /* ARM Erratum 838869 */
#endif /*--------- VFP available */
" BX lr \n" /* return to the preempted task */

21
ports/arm-cm/qk/iar/qk_port.cpp
View File

@ -23,8 +23,8 @@
* <info@state-machine.com>
============================================================================*/
/*!
* @date Last updated on: 2022-12-18
* @version Last updated for: @ref qpc_7_2_0
* @date Last updated on: 2023-01-14
* @version Last updated for: @ref qpc_7_2_1
*
* @file
* @brief QK/C++ port to ARM Cortex-M, IAR-ARM toolset
@ -72,6 +72,7 @@ void NMI_Handler(void);
* changed by the application-level code.
*/
void QK_init(void) {
#if (__ARM_ARCH != 6) /*--------- if ARMv7-M and higher... */
/* set exception priorities to QF_BASEPRI...
@ -103,12 +104,12 @@ void QK_init(void) {
* to return to thread mode (default is to use the NMI exception)
*/
NVIC_IP[QK_USE_IRQ_NUM] = 0U; /* priority 0 (highest) */
NVIC_EN[QK_USE_IRQ_NUM / 32U] = (1U << (QK_USE_IRQ_NUM % 32U));
NVIC_EN[QK_USE_IRQ_NUM >> 5U] = (1U << (QK_USE_IRQ_NUM & 0x1FU));
#endif /*--------- QK IRQ specified */
#if (__ARM_FP != 0) /*--------- if VFP available... */
/* configure the FPU for QK */
FPU_FPCCR |= (1U << 30U) /* automatic FPU state preservation (ASPEN) */
/* configure the FPU for QK: automatic FPU state preservation (ASPEN) */
FPU_FPCCR = FPU_FPCCR | (1U << 30U)
| (1U << 31U); /* lazy stacking (LSPEN) */
#endif /*--------- VFP available */
}
@ -151,7 +152,7 @@ __asm volatile (
" PUSH {r0,lr} \n" /* ... push lr plus stack-aligner */
#endif /*--------- VFP available */
" MOVS r0,#" STRINGIFY(QF_BASEPRI) "\n"
" CPSID i \n" /* disable interrutps with BASEPRI */
" CPSID i \n" /* disable interrupts with BASEPRI */
" MSR BASEPRI,r0 \n" /* apply the Cortex-M7 erraturm */
" CPSIE i \n" /* 837070, see SDEN-1068427. */
#endif /*--------- ARMv7-M and higher */
@ -224,13 +225,9 @@ __asm volatile (
" STR r1,[r0] \n" /* ICSR[31] := 1 (pend NMI) */
#else /*--------- use the selected IRQ */
" LDR r0,=" STRINGIFY(NVIC_PEND + (QK_USE_IRQ_NUM / 32)) "\n"
" LDR r0,=" STRINGIFY(NVIC_PEND + ((QK_USE_IRQ_NUM >> 5) << 2)) "\n"
" MOVS r1,#1 \n"
/* NOTE: the following IRQ bit calculation should be done simply as
* (QK_USE_IRQ_NUM % 32), but the IAR assembler does not accept it.
* As a workaround the modulo (%) operation is replaced with the following:
*/
" LSLS r1,r1,#" STRINGIFY(QK_USE_IRQ_NUM - (QK_USE_IRQ_NUM/32)*32) "\n"
" LSLS r1,r1,#" STRINGIFY(QK_USE_IRQ_NUM & 0x1F) "\n" /* r1 := IRQ bit */
" STR r1,[r0] \n" /* pend the IRQ */
/* now enable interrupts so that pended IRQ can be entered */

4
ports/arm-cm/qv/armclang/qv_port.cpp
View File

@ -86,8 +86,8 @@ void QV_init(void) {
SCB_SYSPRI[3] = (SCB_SYSPRI[3] | (0xFFU << 16U));
#if (__ARM_FP != 0) /*--------- if VFP available... */
/* configure the FPU for QK */
FPU_FPCCR |= (1U << 30U) /* automatic FPU state preservation (ASPEN) */
/* configure the FPU for QV: automatic FPU state preservation (ASPEN) */
FPU_FPCCR = FPU_FPCCR | (1U << 30U)
| (1U << 31U); /* lazy stacking (LSPEN) */
#endif /*--------- VFP available */
}

9
ports/arm-cm/qv/gnu/qv_port.cpp
View File

@ -29,7 +29,7 @@
* @file
* @brief QV/C++ port to ARM Cortex-M, GNU-ARM toolset
*/
/* This QV port is part of the interanl QP implementation */
/* This QV port is part of the internal QP implementation */
#define QP_IMPL 1U
#include "qf_port.hpp"
@ -41,7 +41,8 @@ extern "C" {
#define FPU_FPCCR *((uint32_t volatile *)0xE000EF34U)
/*..........................................................................*/
/* Initialize the exception priorities and IRQ priorities to safe values.
/*
* Initialize the exception priorities and IRQ priorities to safe values.
*
* Description:
* On ARMv7-M or higher, this QK port disables interrupts by means of the
@ -85,8 +86,8 @@ void QV_init(void) {
SCB_SYSPRI[3] = (SCB_SYSPRI[3] | (0xFFU << 16U));
#if (__ARM_FP != 0) /*--------- if VFP available... */
/* configure the FPU for QK */
FPU_FPCCR |= (1U << 30U) /* automatic FPU state preservation (ASPEN) */
/* configure the FPU for QV: automatic FPU state preservation (ASPEN) */
FPU_FPCCR = FPU_FPCCR | (1U << 30U)
| (1U << 31U); /* lazy stacking (LSPEN) */
#endif /*--------- VFP available */
}

7
ports/arm-cm/qv/iar/qv_port.cpp
View File

@ -41,7 +41,8 @@ extern "C" {
#define FPU_FPCCR *((uint32_t volatile *)0xE000EF34U)
/*..........................................................................*/
/* Initialize the exception priorities and IRQ priorities to safe values.
/*
* Initialize the exception priorities and IRQ priorities to safe values.
*
* Description:
* On ARMv7-M or higher, this QK port disables interrupts by means of the
@ -85,8 +86,8 @@ void QV_init(void) {
SCB_SYSPRI[3] = (SCB_SYSPRI[3] | (0xFFU << 16U));
#if (__ARM_FP != 0) /*--------- if VFP available... */
/* configure the FPU for QK */
FPU_FPCCR |= (1U << 30U) /* automatic FPU state preservation (ASPEN) */
/* configure the FPU for QV: automatic FPU state preservation (ASPEN) */
FPU_FPCCR = FPU_FPCCR | (1U << 30U)
| (1U << 31U); /* lazy stacking (LSPEN) */
#endif /*--------- VFP available */
}

26
ports/arm-cm/qxk/armclang/qxk_port.cpp
View File

@ -1,5 +1,5 @@
/*============================================================================
* QXK/C++ Real-Time to ARM Cortex-M, ARM-CLANG
* QP/C++ Real-Time Embedded Framework (RTEF)
* Copyright (C) 2005 Quantum Leaps, LLC. All rights reserved.
*
* SPDX-License-Identifier: GPL-3.0-or-later OR LicenseRef-QL-commercial
@ -23,8 +23,8 @@
* <info@state-machine.com>
============================================================================*/
/*!
* @date Last updated on: 2022-12-18
* @version Last updated for: @ref qpc_7_2_0
* @date Last updated on: 2023-01-14
* @version Last updated for: @ref qpc_7_2_1
*
* @file
* @brief QXK/C++ port to ARM Cortex-M, ARM-CLANG toolset
@ -47,11 +47,11 @@ void QXK_USE_IRQ_HANDLER(void);
void NMI_Handler(void);
#endif
#define SCnSCB_ICTR ((uint32_t volatile *)0xE000E004)
#define SCB_SYSPRI ((uint32_t volatile *)0xE000ED14)
#define NVIC_EN ((uint32_t volatile *)0xE000E100)
#define NVIC_IP ((uint8_t volatile *)0xE000E400)
#define FPU_FPCCR *((uint32_t volatile *)0xE000EF34)
#define SCnSCB_ICTR ((uint32_t volatile *)0xE000E004U)
#define SCB_SYSPRI ((uint32_t volatile *)0xE000ED14U)
#define NVIC_EN ((uint32_t volatile *)0xE000E100U)
#define NVIC_IP ((uint8_t volatile *)0xE000E400U)
#define FPU_FPCCR *((uint32_t volatile *)0xE000EF34U)
#define NVIC_PEND 0xE000E200
#define NVIC_ICSR 0xE000ED04
@ -104,12 +104,12 @@ void QXK_init(void) {
* to return to thread mode (default is to use the NMI exception)
*/
NVIC_IP[QXK_USE_IRQ_NUM] = 0U; /* priority 0 (highest) */
NVIC_EN[QXK_USE_IRQ_NUM / 32U] = (1U << (QXK_USE_IRQ_NUM % 32U));
NVIC_EN[QXK_USE_IRQ_NUM >> 5U] = (1U << (QXK_USE_IRQ_NUM & 0x1FU));
#endif /*--------- QXK IRQ specified */
#if (__ARM_FP != 0) /*--------- if VFP available... */
/* configure the FPU for QK */
FPU_FPCCR |= (1U << 30U) /* automatic FPU state preservation (ASPEN) */
/* configure the FPU for QXK: automatic FPU state preservation (ASPEN) */
FPU_FPCCR = FPU_FPCCR | (1U << 30U)
| (1U << 31U); /* lazy stacking (LSPEN) */
#endif /*--------- VFP available */
}
@ -541,9 +541,9 @@ __asm volatile (
" STR r1,[r0] \n" /* ICSR[31] := 1 (pend NMI) */
#else /*--------- use the selected IRQ */
" LDR r0,=" STRINGIFY(NVIC_PEND + (QXK_USE_IRQ_NUM / 32)) "\n"
" LDR r0,=" STRINGIFY(NVIC_PEND + ((QXK_USE_IRQ_NUM >> 5) << 2)) "\n"
" MOVS r1,#1 \n"
" LSLS r1,r1,#" STRINGIFY(QXK_USE_IRQ_NUM % 32) "\n" /* r1 := IRQ bit */
" LSLS r1,r1,#" STRINGIFY(QXK_USE_IRQ_NUM & 0x1F) "\n" /* r1 := IRQ bit */
" STR r1,[r0] \n" /* pend the IRQ */
/* now enable interrupts so that pended IRQ can be entered */

16
ports/arm-cm/qxk/gnu/qxk_port.cpp
View File

@ -1,5 +1,5 @@
/*============================================================================
* QP/C Real-Time Embedded Framework (RTEF)
* QP/C++ Real-Time Embedded Framework (RTEF)
* Copyright (C) 2005 Quantum Leaps, LLC. All rights reserved.
*
* SPDX-License-Identifier: GPL-3.0-or-later OR LicenseRef-QL-commercial
@ -23,8 +23,8 @@
* <info@state-machine.com>
============================================================================*/
/*!
* @date Last updated on: 2022-12-18
* @version Last updated for: @ref qpc_7_2_0
* @date Last updated on: 2023-01-14
* @version Last updated for: @ref qpc_7_2_1
*
* @file
* @brief QXK/C++ port to ARM Cortex-M, GNU-ARM toolset
@ -104,12 +104,12 @@ void QXK_init(void) {
* to return to thread mode (default is to use the NMI exception)
*/
NVIC_IP[QXK_USE_IRQ_NUM] = 0U; /* priority 0 (highest) */
NVIC_EN[QXK_USE_IRQ_NUM / 32U] = (1U << (QXK_USE_IRQ_NUM % 32U));
NVIC_EN[QXK_USE_IRQ_NUM >> 5U] = (1U << (QXK_USE_IRQ_NUM & 0x1FU));
#endif /*--------- QXK IRQ specified */
#if (__ARM_FP != 0) /*--------- if VFP available... */
/* configure the FPU for QK */
FPU_FPCCR |= (1U << 30U) /* automatic FPU state preservation (ASPEN) */
/* configure the FPU for QXK: automatic FPU state preservation (ASPEN) */
FPU_FPCCR = FPU_FPCCR | (1U << 30U)
| (1U << 31U); /* lazy stacking (LSPEN) */
#endif /*--------- VFP available */
}
@ -546,9 +546,9 @@ __asm volatile (
" STR r1,[r0] \n" /* ICSR[31] := 1 (pend NMI) */
#else /*--------- use the selected IRQ */
" LDR r0,=" STRINGIFY(NVIC_PEND + (QXK_USE_IRQ_NUM / 32)) "\n"
" LDR r0,=" STRINGIFY(NVIC_PEND + ((QXK_USE_IRQ_NUM >> 5) << 2)) "\n"
" MOV r1,#1 \n"
" LSL r1,r1,#" STRINGIFY(QXK_USE_IRQ_NUM % 32) "\n" /* r1 := IRQ bit */
" LSL r1,r1,#" STRINGIFY(QXK_USE_IRQ_NUM & 0x1F) "\n" /* r1 := IRQ bit */
" STR r1,[r0] \n" /* pend the IRQ */
/* now enable interrupts so that pended IRQ can be entered */

20
ports/arm-cm/qxk/iar/qxk_port.cpp
View File

@ -1,5 +1,5 @@
/*============================================================================
* QP/C Real-Time Embedded Framework (RTEF)
* QP/C++ Real-Time Embedded Framework (RTEF)
* Copyright (C) 2005 Quantum Leaps, LLC. All rights reserved.
*
* SPDX-License-Identifier: GPL-3.0-or-later OR LicenseRef-QL-commercial
@ -23,8 +23,8 @@
* <info@state-machine.com>
============================================================================*/
/*!
* @date Last updated on: 2022-12-18
* @version Last updated for: @ref qpc_7_2_0
* @date Last updated on: 2023-01-14
* @version Last updated for: @ref qpc_7_2_1
*
* @file
* @brief QXK/C++ port to ARM Cortex-M, IAR-ARM toolset
@ -104,12 +104,12 @@ void QXK_init(void) {
* to return to thread mode (default is to use the NMI exception)
*/
NVIC_IP[QXK_USE_IRQ_NUM] = 0U; /* priority 0 (highest) */
NVIC_EN[QXK_USE_IRQ_NUM / 32U] = (1U << (QXK_USE_IRQ_NUM % 32U));
NVIC_EN[QXK_USE_IRQ_NUM >> 5U] = (1U << (QXK_USE_IRQ_NUM & 0x1FU));
#endif /*--------- QXK IRQ specified */
#if (__ARM_FP != 0) /*--------- if VFP available... */
/* configure the FPU for QK */
FPU_FPCCR |= (1U << 30U) /* automatic FPU state preservation (ASPEN) */
/* configure the FPU for QXK: automatic FPU state preservation (ASPEN) */
FPU_FPCCR = FPU_FPCCR | (1U << 30U)
| (1U << 31U); /* lazy stacking (LSPEN) */
#endif /*--------- VFP available */
}
@ -541,13 +541,9 @@ __asm volatile (
" STR r1,[r0] \n" /* ICSR[31] := 1 (pend NMI) */
#else /*--------- use the selected IRQ */
" LDR r0,=" STRINGIFY(NVIC_PEND + (QXK_USE_IRQ_NUM / 32)) "\n"
" LDR r0,=" STRINGIFY(NVIC_PEND + ((QXK_USE_IRQ_NUM >> 5) << 2)) "\n"
" MOVS r1,#1 \n"
/* NOTE: the following IRQ bit calculation should be done simply as
* (QXK_USE_IRQ_NUM % 32), but the IAR assembler does not accept it.
* As a workaround the modulo (%) operation is replaced with the following:
*/
" LSLS r1,r1,#" STRINGIFY(QXK_USE_IRQ_NUM - (QXK_USE_IRQ_NUM/32)*32) "\n"
" LSLS r1,r1,#" STRINGIFY(QXK_USE_IRQ_NUM & 0x1F) "\n" /* r1 := IRQ bit */
" STR r1,[r0] \n" /* pend the IRQ */
/* now enable interrupts so that pended IRQ can be entered */