///***************************************************************************
// Product: DPP example, EK-TM4C123GXL board, cooperative QV kernel
// Last updated for version 5.4.0
// Last updated on 2015-05-06
//
// Q u a n t u m L e a P s
// ---------------------------
// innovating embedded systems
//
// Copyright (C) Quantum Leaps, LLC. All rights reserved.
//
// This program is open source software: you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// Alternatively, this program may be distributed and modified under the
// terms of Quantum Leaps commercial licenses, which expressly supersede
// the GNU General Public License and are specifically designed for
// licensees interested in retaining the proprietary status of their code.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see .
//
// Contact information:
// Web: www.state-machine.com
// Email: info@state-machine.com
//****************************************************************************
#include "qpcpp.h"
#include "dpp.h"
#include "bsp.h"
#include "TM4C123GH6PM.h" // the device specific header (TI)
#include "rom.h" // the built-in ROM functions (TI)
#include "sysctl.h" // system control driver (TI)
#include "gpio.h" // GPIO driver (TI)
// add other drivers if necessary...
// namespace DPP *************************************************************
namespace DPP {
Q_DEFINE_THIS_FILE
// !!!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
// Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
// DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!
//
enum KernelUnawareISRs { // see NOTE00
// ...
MAX_KERNEL_UNAWARE_CMSIS_PRI // keep always last
};
// "kernel-unaware" interrupts can't overlap "kernel-aware" interrupts
Q_ASSERT_COMPILE(MAX_KERNEL_UNAWARE_CMSIS_PRI <= QF_AWARE_ISR_CMSIS_PRI);
enum KernelAwareISRs {
GPIOA_PRIO = QF_AWARE_ISR_CMSIS_PRI, // see NOTE00
SYSTICK_PRIO,
// ...
MAX_KERNEL_AWARE_CMSIS_PRI // keep always last
};
// "kernel-aware" interrupts should not overlap the PendSV priority
Q_ASSERT_COMPILE(MAX_KERNEL_AWARE_CMSIS_PRI <= (0xFF >>(8-__NVIC_PRIO_BITS)));
// Local-scope objects -------------------------------------------------------
#define LED_RED (1U << 1)
#define LED_GREEN (1U << 3)
#define LED_BLUE (1U << 2)
#define BTN_SW1 (1U << 4)
#define BTN_SW2 (1U << 0)
static unsigned l_rnd; // random seed
#ifdef Q_SPY
QP::QSTimeCtr QS_tickTime_;
QP::QSTimeCtr QS_tickPeriod_;
static uint8_t l_SysTick_Handler;
static uint8_t l_GPIOPortA_IRQHandler;
#define UART_BAUD_RATE 115200U
#define UART_FR_TXFE 0x80U
#define UART_TXFIFO_DEPTH 16U
enum AppRecords { // application-specific trace records
PHILO_STAT = QP::QS_USER
};
#endif
// ISRs used in this project =================================================
extern "C" {
//............................................................................
void SysTick_Handler(void); // prototype
void SysTick_Handler(void) {
// state of the button debouncing, see below
static struct ButtonsDebouncing {
uint32_t depressed;
uint32_t previous;
} buttons = { ~0U, ~0U };
uint32_t current;
uint32_t tmp;
#ifdef Q_SPY
{
tmp = SysTick->CTRL; // clear SysTick_CTRL_COUNTFLAG
QS_tickTime_ += QS_tickPeriod_; // account for the clock rollover
}
#endif
QP::QF::TICK_X(0U, &l_SysTick_Handler); // process time events for rate 0
// Perform the debouncing of buttons. The algorithm for debouncing
// adapted from the book "Embedded Systems Dictionary" by Jack Ganssle
// and Michael Barr, page 71.
//
current = ~GPIOF->DATA_Bits[BTN_SW1 | BTN_SW2]; // read SW1 and SW2
tmp = buttons.depressed; // save the debounced depressed buttons
buttons.depressed |= (buttons.previous & current); // set depressed
buttons.depressed &= (buttons.previous | current); // clear released
buttons.previous = current; // update the history
tmp ^= buttons.depressed; // changed debounced depressed
if ((tmp & BTN_SW1) != 0U) { // debounced SW1 state changed?
if ((buttons.depressed & BTN_SW1) != 0U) { // is SW1 depressed?
static QP::QEvt const pauseEvt = { DPP::PAUSE_SIG, 0U, 0U};
QP::QF::PUBLISH(&pauseEvt, &l_SysTick_Handler);
}
else { // the button is released
static QP::QEvt const serveEvt = { DPP::SERVE_SIG, 0U, 0U};
QP::QF::PUBLISH(&serveEvt, &l_SysTick_Handler);
}
}
}
//............................................................................
void GPIOPortA_IRQHandler(void); // prototype
void GPIOPortA_IRQHandler(void) {
// for testing..
DPP::AO_Table->POST(Q_NEW(QP::QEvt, DPP::MAX_PUB_SIG),
&l_GPIOPortA_IRQHandler);
}
} // extern "C"
// BSP functions =============================================================
void BSP_init(void) {
// NOTE: SystemInit() already called from the startup code
// but SystemCoreClock needs to be updated
//
SystemCoreClockUpdate();
// configure the FPU usage by choosing one of the options...
#if 1
// OPTION 1:
// Use the automatic FPU state preservation and the FPU lazy stacking.
//
// NOTE:
// Use the following setting when FPU is used in more than one task or
// in any ISRs. This setting is the safest and recommended, but requires
// extra stack space and CPU cycles.
//
FPU->FPCCR |= (1U << FPU_FPCCR_ASPEN_Pos) | (1U << FPU_FPCCR_LSPEN_Pos);
#else
// OPTION 2:
// Do NOT to use the automatic FPU state preservation and
// do NOT to use the FPU lazy stacking.
//
// NOTE:
// Use the following setting when FPU is used in ONE task only and not
// in any ISR. This setting is very efficient, but if more than one task
// (or ISR) start using the FPU, this can lead to corruption of the
// FPU registers. This option should be used with CAUTION.
//
FPU->FPCCR &= ~((1U << FPU_FPCCR_ASPEN_Pos) | (1U << FPU_FPCCR_LSPEN_Pos));
#endif
// enable clock to the peripherals used by the application
SYSCTL->RCGC2 |= (1U << 5); // enable clock to GPIOF
__NOP(); // wait after enabling clocks
__NOP();
__NOP();
// configure the LEDs and push buttons
GPIOF->DIR |= (LED_RED | LED_GREEN | LED_BLUE); // set direction: output
GPIOF->DEN |= (LED_RED | LED_GREEN | LED_BLUE); // digital enable
GPIOF->DATA_Bits[LED_RED] = 0U; // turn the LED off
GPIOF->DATA_Bits[LED_GREEN] = 0U; // turn the LED off
GPIOF->DATA_Bits[LED_BLUE] = 0U; // turn the LED off
// configure the Buttons
GPIOF->DIR &= ~(BTN_SW1 | BTN_SW2); // set direction: input
ROM_GPIOPadConfigSet(GPIOF_BASE, (BTN_SW1 | BTN_SW2),
GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU);
BSP_randomSeed(1234U);
if (!QS_INIT((void *)0)) { // initialize the QS software tracing
Q_ERROR();
}
QS_OBJ_DICTIONARY(&l_SysTick_Handler);
QS_OBJ_DICTIONARY(&l_GPIOPortA_IRQHandler);
}
//............................................................................
void BSP_displayPhilStat(uint8_t n, char const *stat) {
GPIOF->DATA_Bits[LED_RED] = ((stat[0] == 'h') ? 0xFFU : 0U);
GPIOF->DATA_Bits[LED_GREEN] = ((stat[0] == 'e') ? 0xFFU : 0U);
QS_BEGIN(PHILO_STAT, AO_Philo[n]) // application-specific record begin
QS_U8(1, n); // Philosopher number
QS_STR(stat); // Philosopher status
QS_END()
}
//............................................................................
void BSP_displayPaused(uint8_t paused) {
GPIOF->DATA_Bits[LED_RED] = ((paused != 0U) ? 0xFFU : 0U);
}
//............................................................................
uint32_t BSP_random(void) { // a very cheap pseudo-random-number generator
// The flating point code is to exercise the FPU
float volatile x = 3.1415926F;
x = x + 2.7182818F;
// "Super-Duper" Linear Congruential Generator (LCG)
// LCG(2^32, 3*7*11*13*23, 0, seed)
//
l_rnd = l_rnd * (3U*7U*11U*13U*23U);
return l_rnd >> 8;
}
//............................................................................
void BSP_randomSeed(uint32_t seed) {
l_rnd = seed;
}
//............................................................................
void BSP_terminate(int16_t result) {
(void)result;
}
} // namespace DPP
// namespace QP **************************************************************
namespace QP {
// QF callbacks ==============================================================
void QF::onStartup(void) {
// set up the SysTick timer to fire at BSP_TICKS_PER_SEC rate
SysTick_Config(SystemCoreClock / DPP::BSP_TICKS_PER_SEC);
// assing all priority bits for preemption-prio. and none to sub-prio.
NVIC_SetPriorityGrouping(0U);
// set priorities of ALL ISRs used in the system, see NOTE00
//
// !!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
// Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
// DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!
//
NVIC_SetPriority(SysTick_IRQn, DPP::SYSTICK_PRIO);
NVIC_SetPriority(GPIOA_IRQn, DPP::GPIOA_PRIO);
// ...
// enable IRQs...
NVIC_EnableIRQ(GPIOA_IRQn);
}
//............................................................................
void QF::onCleanup(void) {
}
//............................................................................
void QV::onIdle(void) { // called with interrupts disabled, see NOTE01
// toggle the User LED on and then off, see NOTE02
GPIOF->DATA_Bits[LED_BLUE] = 0xFFU; // turn the Blue LED on
GPIOF->DATA_Bits[LED_BLUE] = 0U; // turn the Blue LED off
#ifdef Q_SPY
QF_INT_ENABLE();
if ((UART0->FR & UART_FR_TXFE) != 0U) { // TX done?
uint16_t fifo = UART_TXFIFO_DEPTH; // max bytes we can accept
uint8_t const *block;
QF_INT_DISABLE();
block = QS::getBlock(&fifo); // try to get next block to transmit
QF_INT_ENABLE();
while (fifo-- != 0U) { // any bytes in the block?
UART0->DR = *block++; // put into the FIFO
}
}
#elif defined NDEBUG
// Put the CPU and peripherals to the low-power mode.
// you might need to customize the clock management for your application,
// see the datasheet for your particular Cortex-M MCU.
//
QV_CPU_SLEEP(); // atomically go to sleep and enable interrupts */
#else
QF_INT_ENABLE(); // just enable interrupts */
#endif
}
//............................................................................
// NOTE Q_onAssert() defined in assembly in startup_TM4C123GH6PM.s
// QS callbacks ==============================================================
#ifdef Q_SPY
//............................................................................
bool QS::onStartup(void const *arg) {
static uint8_t qsBuf[2*1024]; // buffer for Quantum Spy
uint32_t tmp;
initBuf(qsBuf, sizeof(qsBuf));
// enable the peripherals used by the UART0
SYSCTL->RCGC1 |= (1U << 0); // enable clock to UART0
SYSCTL->RCGC2 |= (1U << 0); // enable clock to GPIOA
__NOP(); // wait after enabling clocks
__NOP();
__NOP();
// configure UART0 pins for UART operation
tmp = (1U << 0) | (1U << 1);
GPIOA->DIR &= ~tmp;
GPIOA->AFSEL |= tmp;
GPIOA->DR2R |= tmp; // set 2mA drive, DR4R and DR8R are cleared
GPIOA->SLR &= ~tmp;
GPIOA->ODR &= ~tmp;
GPIOA->PUR &= ~tmp;
GPIOA->PDR &= ~tmp;
GPIOA->DEN |= tmp;
// configure the UART for the desired baud rate, 8-N-1 operation
tmp = (((SystemCoreClock * 8U) / UART_BAUD_RATE) + 1U) / 2U;
UART0->IBRD = tmp / 64U;
UART0->FBRD = tmp % 64U;
UART0->LCRH = 0x60U; // configure 8-N-1 operation
UART0->LCRH |= 0x10U;
UART0->CTL |= (1U << 0) | (1U << 8) | (1U << 9);
DPP::QS_tickPeriod_ = SystemCoreClock / DPP::BSP_TICKS_PER_SEC;
DPP::QS_tickTime_ = DPP::QS_tickPeriod_; // to start the timestamp at zero
// setup the QS filters...
QS_FILTER_ON(QS_QEP_STATE_ENTRY);
QS_FILTER_ON(QS_QEP_STATE_EXIT);
QS_FILTER_ON(QS_QEP_STATE_INIT);
QS_FILTER_ON(QS_QEP_INIT_TRAN);
QS_FILTER_ON(QS_QEP_INTERN_TRAN);
QS_FILTER_ON(QS_QEP_TRAN);
QS_FILTER_ON(QS_QEP_IGNORED);
QS_FILTER_ON(QS_QEP_DISPATCH);
QS_FILTER_ON(QS_QEP_UNHANDLED);
// QS_FILTER_ON(QS_QF_ACTIVE_ADD);
// QS_FILTER_ON(QS_QF_ACTIVE_REMOVE);
// QS_FILTER_ON(QS_QF_ACTIVE_SUBSCRIBE);
// QS_FILTER_ON(QS_QF_ACTIVE_UNSUBSCRIBE);
// QS_FILTER_ON(QS_QF_ACTIVE_POST_FIFO);
// QS_FILTER_ON(QS_QF_ACTIVE_POST_LIFO);
// QS_FILTER_ON(QS_QF_ACTIVE_GET);
// QS_FILTER_ON(QS_QF_ACTIVE_GET_LAST);
// QS_FILTER_ON(QS_QF_EQUEUE_INIT);
// QS_FILTER_ON(QS_QF_EQUEUE_POST_FIFO);
// QS_FILTER_ON(QS_QF_EQUEUE_POST_LIFO);
// QS_FILTER_ON(QS_QF_EQUEUE_GET);
// QS_FILTER_ON(QS_QF_EQUEUE_GET_LAST);
// QS_FILTER_ON(QS_QF_MPOOL_INIT);
// QS_FILTER_ON(QS_QF_MPOOL_GET);
// QS_FILTER_ON(QS_QF_MPOOL_PUT);
// QS_FILTER_ON(QS_QF_PUBLISH);
// QS_FILTER_ON(QS_QF_RESERVED8);
// QS_FILTER_ON(QS_QF_NEW);
// QS_FILTER_ON(QS_QF_GC_ATTEMPT);
// QS_FILTER_ON(QS_QF_GC);
QS_FILTER_ON(QS_QF_TICK);
// QS_FILTER_ON(QS_QF_TIMEEVT_ARM);
// QS_FILTER_ON(QS_QF_TIMEEVT_AUTO_DISARM);
// QS_FILTER_ON(QS_QF_TIMEEVT_DISARM_ATTEMPT);
// QS_FILTER_ON(QS_QF_TIMEEVT_DISARM);
// QS_FILTER_ON(QS_QF_TIMEEVT_REARM);
// QS_FILTER_ON(QS_QF_TIMEEVT_POST);
// QS_FILTER_ON(QS_QF_TIMEEVT_CTR);
// QS_FILTER_ON(QS_QF_CRIT_ENTRY);
// QS_FILTER_ON(QS_QF_CRIT_EXIT);
// QS_FILTER_ON(QS_QF_ISR_ENTRY);
// QS_FILTER_ON(QS_QF_ISR_EXIT);
// QS_FILTER_ON(QS_QF_INT_DISABLE);
// QS_FILTER_ON(QS_QF_INT_ENABLE);
// QS_FILTER_ON(QS_QF_ACTIVE_POST_ATTEMPT);
// QS_FILTER_ON(QS_QF_EQUEUE_POST_ATTEMPT);
// QS_FILTER_ON(QS_QF_MPOOL_GET_ATTEMPT);
// QS_FILTER_ON(QS_QF_RESERVED1);
// QS_FILTER_ON(QS_QF_RESERVED0);
// QS_FILTER_ON(QS_QK_MUTEX_LOCK);
// QS_FILTER_ON(QS_QK_MUTEX_UNLOCK);
// QS_FILTER_ON(QS_QK_SCHEDULE);
// QS_FILTER_ON(QS_QK_RESERVED1);
// QS_FILTER_ON(QS_QK_RESERVED0);
// QS_FILTER_ON(QS_QEP_TRAN_HIST);
// QS_FILTER_ON(QS_QEP_TRAN_EP);
// QS_FILTER_ON(QS_QEP_TRAN_XP);
// QS_FILTER_ON(QS_QEP_RESERVED1);
// QS_FILTER_ON(QS_QEP_RESERVED0);
QS_FILTER_ON(QS_SIG_DICT);
QS_FILTER_ON(QS_OBJ_DICT);
QS_FILTER_ON(QS_FUN_DICT);
QS_FILTER_ON(QS_USR_DICT);
QS_FILTER_ON(QS_EMPTY);
QS_FILTER_ON(QS_RESERVED3);
QS_FILTER_ON(QS_RESERVED2);
QS_FILTER_ON(QS_TEST_RUN);
QS_FILTER_ON(QS_TEST_FAIL);
QS_FILTER_ON(QS_ASSERT_FAIL);
return true; // return success
}
//............................................................................
void QS::onCleanup(void) {
}
//............................................................................
QSTimeCtr QS::onGetTime(void) { // NOTE: invoked with interrupts DISABLED
if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0) { // not set?
return DPP::QS_tickTime_ - static_cast(SysTick->VAL);
}
else { // the rollover occured, but the SysTick_ISR did not run yet
return DPP::QS_tickTime_ + DPP::QS_tickPeriod_
- static_cast(SysTick->VAL);
}
}
//............................................................................
void QS::onFlush(void) {
uint16_t fifo = UART_TXFIFO_DEPTH; // Tx FIFO depth
uint8_t const *block;
QF_INT_DISABLE();
while ((block = getBlock(&fifo)) != static_cast(0)) {
QF_INT_ENABLE();
// busy-wait until TX FIFO empty
while ((UART0->FR & UART_FR_TXFE) == 0U) {
}
while (fifo-- != 0U) { // any bytes in the block?
UART0->DR = *block++; // put into the TX FIFO
}
fifo = UART_TXFIFO_DEPTH; // re-load the Tx FIFO depth
QF_INT_DISABLE();
}
QF_INT_ENABLE();
}
#endif // Q_SPY
//--------------------------------------------------------------------------*/
} // namespace QP
//****************************************************************************
// NOTE00:
// The QF_AWARE_ISR_CMSIS_PRI constant from the QF port specifies the highest
// ISR priority that is disabled by the QF framework. The value is suitable
// for the NVIC_SetPriority() CMSIS function.
//
// Only ISRs prioritized at or below the QF_AWARE_ISR_CMSIS_PRI level (i.e.,
// with the numerical values of priorities equal or higher than
// QF_AWARE_ISR_CMSIS_PRI) are allowed to call the QK_ISR_ENTRY/QK_ISR_ENTRY
// macros or any other QF/QK services. These ISRs are "QF-aware".
//
// Conversely, any ISRs prioritized above the QF_AWARE_ISR_CMSIS_PRI priority
// level (i.e., with the numerical values of priorities less than
// QF_AWARE_ISR_CMSIS_PRI) are never disabled and are not aware of the kernel.
// Such "QF-unaware" ISRs cannot call any QF/QK services. In particular they
// can NOT call the macros QK_ISR_ENTRY/QK_ISR_ENTRY. The only mechanism
// by which a "QF-unaware" ISR can communicate with the QF framework is by
// triggering a "QF-aware" ISR, which can post/publish events.
//
// NOTE01:
// The QV:onIdle() callback is called with interrupts disabled, because the
// determination of the idle condition might change by any interrupt posting
// an event. QV::onIdle() must internally enable interrupts, ideally
// atomically with putting the CPU to the power-saving mode.
//
// NOTE02:
// The User LED is used to visualize the idle loop activity. The brightness
// of the LED is proportional to the frequency of invcations of the idle loop.
// Please note that the LED is toggled with interrupts locked, so no interrupt
// execution time contributes to the brightness of the User LED.
//