///***************************************************************************
// Product: DPP example, STM32 NUCLEO-L053R8 board, preemptive QXK kernel
// Last updated for version 5.9.5
// Last updated on 2017-07-20
//
// Q u a n t u m L e a P s
// ---------------------------
// innovating embedded systems
//
// Copyright (C) Quantum Leaps, LLC. All rights reserved.
//
// This program is open source software: you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// Alternatively, this program may be distributed and modified under the
// terms of Quantum Leaps commercial licenses, which expressly supersede
// the GNU General Public License and are specifically designed for
// licensees interested in retaining the proprietary status of their code.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see .
//
// Contact information:
// https://state-machine.com
// mailto:info@state-machine.com
//****************************************************************************
#include "qpcpp.h"
#include "dpp.h"
#include "bsp.h"
#include "stm32l0xx.h" // CMSIS-compliant header file for the MCU used
// add other drivers if necessary...
Q_DEFINE_THIS_FILE
// namespace DPP *************************************************************
namespace DPP {
// !!!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
// Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
// DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!
//
enum KernelUnawareISRs { // see NOTE00
// ...
MAX_KERNEL_UNAWARE_CMSIS_PRI // keep always last
};
// "kernel-unaware" interrupts can't overlap "kernel-aware" interrupts
Q_ASSERT_COMPILE(MAX_KERNEL_UNAWARE_CMSIS_PRI <= QF_AWARE_ISR_CMSIS_PRI);
enum KernelAwareISRs {
EXTI0_1_PRIO = QF_AWARE_ISR_CMSIS_PRI, // see NOTE00
SYSTICK_PRIO,
// ...
MAX_KERNEL_AWARE_CMSIS_PRI // keep always last
};
// "kernel-aware" interrupts should not overlap the PendSV priority
Q_ASSERT_COMPILE(MAX_KERNEL_AWARE_CMSIS_PRI <= (0xFF >>(8-__NVIC_PRIO_BITS)));
// Local-scope objects -------------------------------------------------------
// LED pins available on the board (just one user LED LD2--Green on PA.5)
#define LED_LD2 (1U << 5)
// Button pins available on the board (just one user Button B1 on PC.13)
#define BTN_B1 (1U << 13)
static unsigned l_rnd; // random seed
static QP::QXMutex l_rndMutex; // to protect the random number generator
#ifdef Q_SPY
QP::QSTimeCtr QS_tickTime_;
QP::QSTimeCtr QS_tickPeriod_;
// event-source identifiers used for tracing
static uint8_t const l_SysTick_Handler = 0U;
static uint8_t const l_EXTI0_1_IRQHandler = 0U;
enum AppRecords { // application-specific trace records
PHILO_STAT = QP::QS_USER
};
#endif
// ISRs used in this project =================================================
extern "C" {
//............................................................................
void SysTick_Handler(void); // prototype
void SysTick_Handler(void) {
// state of the button debouncing, see below
static struct ButtonsDebouncing {
uint32_t depressed;
uint32_t previous;
} buttons = { ~0U, ~0U };
uint32_t current;
uint32_t tmp;
QXK_ISR_ENTRY(); // inform QXK about entering an ISR
#ifdef Q_SPY
{
tmp = SysTick->CTRL; // clear SysTick_CTRL_COUNTFLAG
QS_tickTime_ += QS_tickPeriod_; // account for the clock rollover
}
#endif
QP::QF::TICK_X(0U, &l_SysTick_Handler); // process time events for rate 0
// Perform the debouncing of buttons. The algorithm for debouncing
// adapted from the book "Embedded Systems Dictionary" by Jack Ganssle
// and Michael Barr, page 71.
//
current = ~GPIOC->IDR; // read Port C with the state of Button B1
tmp = buttons.depressed; // save the debounced depressed buttons
buttons.depressed |= (buttons.previous & current); // set depressed
buttons.depressed &= (buttons.previous | current); // clear released
buttons.previous = current; // update the history
tmp ^= buttons.depressed; // changed debounced depressed
if ((tmp & BTN_B1) != 0U) { // debounced BTN_B1 state changed?
if ((buttons.depressed & BTN_B1) != 0U) { // is BTN_B1 depressed?
static QP::QEvt const pauseEvt = { DPP::PAUSE_SIG, 0U, 0U};
QP::QF::PUBLISH(&pauseEvt, &l_SysTick_Handler);
}
else { // the button is released
static QP::QEvt const serveEvt = { DPP::SERVE_SIG, 0U, 0U};
QP::QF::PUBLISH(&serveEvt, &l_SysTick_Handler);
}
}
QXK_ISR_EXIT(); // inform QXK about exiting an ISR
}
//............................................................................
void EXTI0_1_IRQHandler(void); // prototype
void EXTI0_1_IRQHandler(void) {
QXK_ISR_ENTRY(); // inform QXK about entering an ISR
// for testing..
DPP::AO_Table->POST(Q_NEW(QP::QEvt, DPP::MAX_PUB_SIG),
&l_EXTI0_1_IRQHandler);
QXK_ISR_EXIT(); // inform QXK about exiting an ISR
}
} // extern "C"
// BSP functions =============================================================
void BSP::init(void) {
// NOTE: SystemInit() already called from the startup code
// but SystemCoreClock needs to be updated
//
SystemCoreClockUpdate();
// enable GPIOA clock port for the LED LD2
RCC->IOPENR |= (1U << 0);
// configure LED (PA.5) pin as push-pull output, no pull-up, pull-down
GPIOA->MODER &= ~((3U << 2*5));
GPIOA->MODER |= ((1U << 2*5));
GPIOA->OTYPER &= ~((1U << 5));
GPIOA->OSPEEDR &= ~((3U << 2*5));
GPIOA->OSPEEDR |= ((1U << 2*5));
GPIOA->PUPDR &= ~((3U << 2*5));
// enable GPIOC clock port for the Button B1
RCC->IOPENR |= (1U << 2);
// configure Button (PC.13) pins as input, no pull-up, pull-down
GPIOC->MODER &= ~(3U << 2*13);
GPIOC->OSPEEDR &= ~(3U << 2*13);
GPIOC->OSPEEDR |= (1U << 2*13);
GPIOC->PUPDR &= ~(3U << 2*13);
BSP::randomSeed(1234U);
if (QS_INIT((void *)0) == 0U) { // initialize the QS software tracing
Q_ERROR();
}
QS_OBJ_DICTIONARY(&l_SysTick_Handler);
QS_OBJ_DICTIONARY(&l_EXTI0_1_IRQHandler);
QS_USR_DICTIONARY(PHILO_STAT);
}
//............................................................................
void BSP::displayPhilStat(uint8_t n, char const *stat) {
if (stat[0] == 'h') {
GPIOA->BSRR |= LED_LD2; // turn LED on
}
else {
GPIOA->BSRR |= (LED_LD2 << 16); // turn LED off
}
QS_BEGIN(PHILO_STAT, AO_Philo[n]) // application-specific record begin
QS_U8(1, n); // Philosopher number
QS_STR(stat); // Philosopher status
QS_END()
}
//............................................................................
void BSP::displayPaused(uint8_t paused) {
// not enough LEDs to implement this feature
if (paused != (uint8_t)0) {
//GPIOA->BSRR |= (LED_LD2); // turn LED[n] on
}
else {
//GPIOA->BSRR |= (LED_LD2 << 16); // turn LED[n] off
}
}
//............................................................................
uint32_t BSP::random(void) { // a very cheap pseudo-random-number generator
l_rndMutex.lock(); // lock the shared random seed
// "Super-Duper" Linear Congruential Generator (LCG)
// LCG(2^32, 3*7*11*13*23, 0, seed)
//
uint32_t rnd = l_rnd * (3U*7U*11U*13U*23U);
l_rnd = rnd; // set for the next time
l_rndMutex.unlock(); // unlock the shared random seed
return (rnd >> 8);
}
//............................................................................
void BSP::randomSeed(uint32_t seed) {
l_rndMutex.init(N_PHILO + 1U);
l_rnd = seed;
}
//............................................................................
void BSP::ledOn(void) {
GPIOA->BSRR |= (LED_LD2); // turn LED2 on
}
//............................................................................
void BSP::ledOff(void) {
GPIOA->BSRR |= (LED_LD2 << 16); // turn LED2 off
}
//............................................................................
void BSP::terminate(int16_t result) {
(void)result;
}
} // namespace DPP
// namespace QP **************************************************************
namespace QP {
// QF callbacks ==============================================================
void QF::onStartup(void) {
// set up the SysTick timer to fire at BSP::TICKS_PER_SEC rate
SysTick_Config(SystemCoreClock / DPP::BSP::TICKS_PER_SEC);
// set priorities of ALL ISRs used in the system, see NOTE00
//
// !!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
// Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
// DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!
//
NVIC_SetPriority(SysTick_IRQn, DPP::SYSTICK_PRIO);
NVIC_SetPriority(EXTI0_1_IRQn, DPP::EXTI0_1_PRIO);
// ...
// enable IRQs...
NVIC_EnableIRQ(EXTI0_1_IRQn);
}
//............................................................................
void QF::onCleanup(void) {
}
//............................................................................
void QXK::onIdle(void) {
// toggle the User LED on and then off (not enough LEDs, see NOTE01)
QF_INT_DISABLE();
//GPIOA->BSRR |= (LED_LD2); // turn LED[n] on
//GPIOA->BSRR |= (LED_LD2 << 16); // turn LED[n] off
QF_INT_ENABLE();
#ifdef Q_SPY
if ((USART2->ISR & 0x0080U) != 0) { // is TXE empty?
QF_INT_DISABLE();
uint16_t b = QS::getByte();
QF_INT_ENABLE();
if (b != QS_EOD) { // not End-Of-Data?
USART2->TDR = (b & 0xFFU); // put into the DR register
}
}
#elif defined NDEBUG
// Put the CPU and peripherals to the low-power mode.
// you might need to customize the clock management for your application,
// see the datasheet for your particular Cortex-M3 MCU.
//
// !!!CAUTION!!!
// The WFI instruction stops the CPU clock, which unfortunately disables
// the JTAG port, so the ST-Link debugger can no longer connect to the
// board. For that reason, the call to __WFI() has to be used with CAUTION.
//
// NOTE: If you find your board "frozen" like this, strap BOOT0 to VDD and
// reset the board, then connect with ST-Link Utilities and erase the part.
// The trick with BOOT(0) is it gets the part to run the System Loader
// instead of your broken code. When done disconnect BOOT0, and start over.
//
//__WFI(); Wait-For-Interrupt
#endif
}
//............................................................................
extern "C" void Q_onAssert(char const *module, int loc) {
//
// NOTE: add here your application-specific error handling
//
(void)module;
(void)loc;
QS_ASSERTION(module, loc, static_cast(10000U));
NVIC_SystemReset();
}
// QS callbacks ==============================================================
#ifdef Q_SPY
/*..........................................................................*/
#define __DIV(__PCLK, __BAUD) (((__PCLK / 4U) * 25U)/(__BAUD))
#define __DIVMANT(__PCLK, __BAUD) (__DIV(__PCLK, __BAUD)/100U)
#define __DIVFRAQ(__PCLK, __BAUD) \
(((__DIV(__PCLK, __BAUD) - (__DIVMANT(__PCLK, __BAUD) * 100U)) \
* 16U + 50U) / 100U)
#define __USART_BRR(__PCLK, __BAUD) \
((__DIVMANT(__PCLK, __BAUD) << 4)|(__DIVFRAQ(__PCLK, __BAUD) & 0x0FU))
//............................................................................
bool QS::onStartup(void const *arg) {
static uint8_t qsBuf[2*1024]; // buffer for Quantum Spy
initBuf(qsBuf, sizeof(qsBuf));
// enable peripheral clock for USART2
RCC->IOPENR |= ( 1ul << 0); // Enable GPIOA clock
RCC->APB1ENR |= ( 1ul << 17); // Enable USART#2 clock
// Configure PA3 to USART2_RX, PA2 to USART2_TX */
GPIOA->AFR[0] &= ~((15ul << 4* 3) | (15ul << 4* 2) );
GPIOA->AFR[0] |= (( 4ul << 4* 3) | ( 4ul << 4* 2) );
GPIOA->MODER &= ~(( 3ul << 2* 3) | ( 3ul << 2* 2) );
GPIOA->MODER |= (( 2ul << 2* 3) | ( 2ul << 2* 2) );
USART2->BRR = __USART_BRR(SystemCoreClock, 115200ul); // baud rate
USART2->CR3 = 0x0000; // no flow control
USART2->CR2 = 0x0000; // 1 stop bit
USART2->CR1 = ((1ul << 2) | // enable RX
(1ul << 3) | // enable TX
(0ul << 12) | // 8 data bits
(0ul << 28) | // 8 data bits
(1ul << 0) ); // enable USART
DPP::QS_tickPeriod_ = SystemCoreClock / DPP::BSP::TICKS_PER_SEC;
DPP::QS_tickTime_ = DPP::QS_tickPeriod_; // to start the timestamp at zero
// setup the QS filters...
QS_FILTER_ON(QS_QEP_STATE_ENTRY);
QS_FILTER_ON(QS_QEP_STATE_EXIT);
QS_FILTER_ON(QS_QEP_STATE_INIT);
QS_FILTER_ON(QS_QEP_INIT_TRAN);
QS_FILTER_ON(QS_QEP_INTERN_TRAN);
QS_FILTER_ON(QS_QEP_TRAN);
QS_FILTER_ON(QS_QEP_IGNORED);
QS_FILTER_ON(QS_QEP_DISPATCH);
QS_FILTER_ON(QS_QEP_UNHANDLED);
QS_FILTER_ON(DPP::PHILO_STAT);
return true; // return success
}
//............................................................................
void QS::onCleanup(void) {
}
//............................................................................
QSTimeCtr QS::onGetTime(void) { // NOTE: invoked with interrupts DISABLED
if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0) { // not set?
return DPP::QS_tickTime_ - static_cast(SysTick->VAL);
}
else { // the rollover occured, but the SysTick_ISR did not run yet
return DPP::QS_tickTime_ + DPP::QS_tickPeriod_
- static_cast(SysTick->VAL);
}
}
//............................................................................
void QS::onFlush(void) {
uint16_t b;
QF_INT_DISABLE();
while ((b = getByte()) != QS_EOD) { // while not End-Of-Data...
QF_INT_ENABLE();
while ((USART2->ISR & 0x0080U) == 0U) { // while TXE not empty
}
USART2->TDR = (b & 0xFFU); // put into the DR register
QF_INT_DISABLE();
}
QF_INT_ENABLE();
}
//............................................................................
//! callback function to reset the target (to be implemented in the BSP)
void QS::onReset(void) {
//TBD
}
//............................................................................
//! callback function to execute a uesr command (to be implemented in BSP)
void QS::onCommand(uint8_t cmdId, uint32_t param1,
uint32_t param2, uint32_t param3)
{
(void)cmdId;
(void)param1;
(void)param2;
(void)param3;
//TBD
}
#endif // Q_SPY
//--------------------------------------------------------------------------*/
} // namespace QP
//****************************************************************************
// NOTE00:
// The QF_AWARE_ISR_CMSIS_PRI constant from the QF port specifies the highest
// ISR priority that is disabled by the QF framework. The value is suitable
// for the NVIC_SetPriority() CMSIS function.
//
// Only ISRs prioritized at or below the QF_AWARE_ISR_CMSIS_PRI level (i.e.,
// with the numerical values of priorities equal or higher than
// QF_AWARE_ISR_CMSIS_PRI) are allowed to call the QK_ISR_ENTRY/QK_ISR_ENTRY
// macros or any other QF/QK services. These ISRs are "QF-aware".
//
// Conversely, any ISRs prioritized above the QF_AWARE_ISR_CMSIS_PRI priority
// level (i.e., with the numerical values of priorities less than
// QF_AWARE_ISR_CMSIS_PRI) are never disabled and are not aware of the kernel.
// Such "QF-unaware" ISRs cannot call any QF/QK services. In particular they
// can NOT call the macros QK_ISR_ENTRY/QK_ISR_ENTRY. The only mechanism
// by which a "QF-unaware" ISR can communicate with the QF framework is by
// triggering a "QF-aware" ISR, which can post/publish events.
//
// NOTE01:
// The User LED is used to visualize the idle loop activity. The brightness
// of the LED is proportional to the frequency of invcations of the idle loop.
// Please note that the LED is toggled with interrupts locked, so no interrupt
// execution time contributes to the brightness of the User LED.
//