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203 lines
8.6 KiB
C++
203 lines
8.6 KiB
C++
//****************************************************************************
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// Product: Simple Blinky example, Tiva EK-TM4C123GXL, Vanilla kernel
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// Last Updated for Version: 5.2.0
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// Date of the Last Update: Dec 28, 2013
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//
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// Q u a n t u m L e a P s
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// ---------------------------
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// innovating embedded systems
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//
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// Copyright (C) 2002-2013 Quantum Leaps, LLC. All rights reserved.
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//
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// This program is open source software: you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// Alternatively, this program may be distributed and modified under the
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// terms of Quantum Leaps commercial licenses, which expressly supersede
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// the GNU General Public License and are specifically designed for
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// licensees interested in retaining the proprietary status of their code.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// Contact information:
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// Quantum Leaps Web sites: http://www.quantum-leaps.com
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// http://www.state-machine.com
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// e-mail: info@quantum-leaps.com
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//****************************************************************************
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#include "qp_port.h"
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#include "bsp.h"
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extern "C" {
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#include "tm4c_cmsis.h" // Tiva-C CMSIS-compliant interface
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#include "sysctl.h"
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#include "gpio.h"
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#include "rom.h"
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}
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using namespace QP;
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Q_DEFINE_THIS_FILE
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//!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
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// Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
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// DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!
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//
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enum KernelUnawareISRs { // see NOTE00
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// ...
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MAX_KERNEL_UNAWARE_CMSIS_PRI // keep always last
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};
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// "kernel-unaware" interrupts can't overlap "kernel-aware" interrupts
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Q_ASSERT_COMPILE(MAX_KERNEL_UNAWARE_CMSIS_PRI <= QF_AWARE_ISR_CMSIS_PRI);
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enum KernelAwareISRs {
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SYSTICK_PRIO = QF_AWARE_ISR_CMSIS_PRI, // see NOTE00
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// ...
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MAX_KERNEL_AWARE_CMSIS_PRI // keep always last
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};
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// "kernel-aware" interrupts should not overlap the PendSV priority
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Q_ASSERT_COMPILE(MAX_KERNEL_AWARE_CMSIS_PRI <= (0xFF >>(8-__NVIC_PRIO_BITS)));
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// LEDs and Switches of the EK-TM4C123GXL board ..............................
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#define LED_RED (1U << 1)
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#define LED_GREEN (1U << 3)
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#define LED_BLUE (1U << 2)
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#define USR_SW1 (1U << 4)
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#define USR_SW2 (1U << 0)
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// ISRs defined in this BSP --------------------------------------------------
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extern "C" void SysTick_Handler(void);
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//............................................................................
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extern "C" void SysTick_Handler(void) { // system clock tick ISR
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QF::TICK_X(0U, (void *)0); // process all armed time events
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}
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//............................................................................
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void BSP_init(void) {
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// Enable the floating-point unit
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SCB->CPACR |= (0xFU << 20);
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// Enable lazy stacking for interrupt handlers. This allows FPU
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// instructions to be used within interrupt handlers, but at the
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// expense of extra stack and CPU usage.
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//
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FPU->FPCCR |= (1U << FPU_FPCCR_ASPEN_Pos) | (1U << FPU_FPCCR_LSPEN_Pos);
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// Set the clocking to run directly from the crystal
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ROM_SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_OSC
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| SYSCTL_OSC_MAIN | SYSCTL_XTAL_16MHZ);
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// enable clock to the peripherals used by the application
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SYSCTL->RCGC2 |= (1U << 5); // enable clock to GPIOF
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__NOP(); // wait after enabling clocks
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__NOP();
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__NOP();
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// configure the LEDs and push buttons
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GPIOF->DIR |= (LED_RED | LED_GREEN | LED_BLUE); // set direction: output
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GPIOF->DEN |= (LED_RED | LED_GREEN | LED_BLUE); // digital enable
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GPIOF->DATA_Bits[LED_RED] = 0; // turn the LED off
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GPIOF->DATA_Bits[LED_GREEN] = 0; // turn the LED off
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GPIOF->DATA_Bits[LED_BLUE] = 0; // turn the LED off
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// configure the User Switches
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GPIOF->DIR &= ~(USR_SW1 | USR_SW2); // set direction: input
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ROM_GPIOPadConfigSet(GPIO_PORTF_BASE, (USR_SW1 | USR_SW2),
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GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU);
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if (QS_INIT((void *)0) == 0) { // initialize the QS software tracing
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Q_ERROR();
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}
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QS_OBJ_DICTIONARY(&l_SysTick_Handler);
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}
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//............................................................................
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void BSP_ledOff() {
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GPIOF->DATA_Bits[LED_GREEN] = 0U;
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}
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//............................................................................
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void BSP_ledOn() {
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GPIOF->DATA_Bits[LED_GREEN] = LED_GREEN;
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}
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//............................................................................
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void QF::onStartup(void) {
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// set up the SysTick timer to fire at BSP_TICKS_PER_SEC rate
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SysTick_Config(ROM_SysCtlClockGet() / BSP_TICKS_PER_SEC);
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// assing all priority bits for preemption-prio. and none to sub-prio.
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NVIC_SetPriorityGrouping(0U);
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// set priorities of ALL ISRs used in the system, see NOTE00
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//
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// !!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
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// Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
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// DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!
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//
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NVIC_SetPriority(SysTick_IRQn, SYSTICK_PRIO);
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// ...
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// enable IRQs...
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}
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//............................................................................
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void QF::onCleanup(void) {
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}
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//............................................................................
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void QF::onIdle(void) { // called with interrupts disabled, see NOTE01
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#ifdef NDEBUG
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// Put the CPU and peripherals to the low-power mode.
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// you might need to customize the clock management for your application,
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// see the datasheet for your particular Cortex-M MCU.
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//
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QF_CPU_SLEEP(); // atomically go to sleep and enable interrupts
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#else
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QF_INT_ENABLE(); // just enable interrupts
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#endif
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}
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//............................................................................
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extern "C" void Q_onAssert(char const Q_ROM * const file, int_t line) {
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assert_failed(file, line);
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}
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//............................................................................
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// error routine that is called if the CMSIS library encounters an error
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extern "C" void assert_failed(char const *file, int line) {
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(void)file; // avoid compiler warning
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(void)line; // avoid compiler warning
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QF_INT_DISABLE(); // make sure that all interrupts are disabled
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ROM_SysCtlReset(); // reset the system
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}
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//****************************************************************************
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// NOTE00:
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// The QF_AWARE_ISR_CMSIS_PRI constant from the QF port specifies the highest
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// ISR priority that is disabled by the QF framework. The value is suitable
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// for the NVIC_SetPriority() CMSIS function.
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//
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// Only ISRs prioritized at or below the QF_AWARE_ISR_CMSIS_PRI level (i.e.,
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// with the numerical values of priorities equal or higher than
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// QF_AWARE_ISR_CMSIS_PRI) are allowed to call any QF services. These ISRs
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// are "QF-aware".
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//
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// Conversely, any ISRs prioritized above the QF_AWARE_ISR_CMSIS_PRI priority
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// level (i.e., with the numerical values of priorities less than
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// QF_AWARE_ISR_CMSIS_PRI) are never disabled and are not aware of the kernel.
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// Such "QF-unaware" ISRs cannot call any QF services. The only mechanism
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// by which a "QF-unaware" ISR can communicate with the QF framework is by
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// triggering a "QF-aware" ISR, which can post/publish events.
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//
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// NOTE01:
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// The QF::onIdle() callback is called with interrupts disabled, because the
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// determination of the idle condition might change by any interrupt posting
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// an event. QF::onIdle() must internally enable interrupts, ideally
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// atomically with putting the CPU to the power-saving mode.
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//
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