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https://github.com/QuantumLeaps/qpcpp.git
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305 lines
12 KiB
C
305 lines
12 KiB
C
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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//****************************************************************************
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// Modified by Quantum Leaps on 09-Mar-2010
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// www.state-machine.com
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//
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// - Added Stellaris DID0 register macros (Stellaris classes and versions)
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// - Configured for EK-LM3S811 board:
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// PLL driven system clock at 20MHz (200 MHz / 10)
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// 6 MHz oscillator
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//****************************************************************************
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//****************************************************************************
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//
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// lm3_config.h - Configuration header file for CMSIS application for
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// Luminary Micro LM3S Stellaris microcontrollers.
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//
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// Copyright (c) 2009 Luminary Micro, Inc. All rights reserved.
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// Software License Agreement
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//
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// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
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// exclusively on LMI's microcontroller products.
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//
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// The software is owned by LMI and/or its suppliers, and is protected under
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// applicable copyright laws. All rights are reserved. You may not combine
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// this software with "viral" open-source software in order to form a larger
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// program. Any use in violation of the foregoing restrictions may subject
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// the user to criminal sanctions under applicable laws, as well as to civil
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// liability for the breach of the terms and conditions of this license.
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//
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// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS
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// SOFTWARE. LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
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// INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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//
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// This is part of revision 32 of the Stellaris CMSIS Package.
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//
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//****************************************************************************
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#ifndef __LM3S_CONFIG_H__
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#define __LM3S_CONFIG_H__
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//
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// This file can be used by the Keil uVision configuration wizard to set
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// the following system clock configuration values. Or the value of the
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// macros can be directly edited below if not using the uVision configuration
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// wizard.
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//
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//--------------------- Clock Configuration ----------------------------------
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//
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// <e> Clock Configuration
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// <i> Uncheck this box to skip the clock configuration.
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//
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// The following controls whether the system clock is configured in the
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// SystemInit() function. If it is defined to be 1 then the system clock
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// will be configured according to the macros in the rest of this file.
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// If it is defined to be 0, then the system clock configuration is bypassed.
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//
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#define CLOCK_SETUP 1
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//********************************* RCC **************************************
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//
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// <h> Run-Mode Clock Configuration (RCC)
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// <o> SYSDIV: System Clock Divisor <2-16>
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// <i> Specifies the divisor used to generate the system clock from
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// <i> either the PLL output of 200 MHz, or the chosen oscillator.
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//
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// The following value is the system clock divisor. This will be applied if
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// USESYSDIV (see below) is enabled. The valid range of dividers is 2-16.
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//
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#define CFG_RCC_SYSDIV 10
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// <q> USESYSDIV: Enable System Clock Divider
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// <i> Check this box to use the System Clock Divider
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//
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// The following controls whether the system clock divider is used. If the
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// value is 1, then the system clock divider is used, and the value of the
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// system divider is defined by SYSDIV (see above). If the value is 0, then
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// the system clock divider is not used.
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//
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#define CFG_RCC_USESYSDIV 1
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// <q> USEPWMDIV: Enable PWM Clock Divider
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// <i> Check this box to use the PWM Clock Divider
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//
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// The following controls whether the PWM clock divider is used. If the
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// value is 1, then the PWM clock divider is used, and the value of the
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// PWM divider is defined by PWMDIV (see below). If the value is 0, then
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// the PWM clock divider is not used.
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//
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#define CFG_RCC_USEPWMDIV 0
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// <o> PWMDIV: PWM Unit Clock Divisor
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// <0=> 0: SysClk / 2
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// <1=> 1: SysClk / 4
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// <2=> 2: SysClk / 8
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// <3=> 3: SysClk / 16
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// <4=> 4: SysClk / 32
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// <5=> 5: SysClk / 64
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// <6=> 6: SysClk / 64
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// <7=> 7: SysClk / 64 (default)
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// <i> Specifies the divisor used to generate the PWM time base,
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// <i> from the System Clock
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//
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// The following value determines the PWM clock divider. It is used if
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// USEPWMDIV is enabled (see above). Otherwise the PWM clock is the same as
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// the system clock. The value of the divider is determined by the table
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// above.
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//
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#define CFG_RCC_PWMDIV 7
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// <q> PWRDN: PLL Power Down
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// <i> Check this box to disable the PLL. You must also choose
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// <i> PLL Bypass.
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//
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// If the following value is 1, then the PLL is powered down. Keep this value
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// as 1 if you do not need to use the PLL. In this case, BYPASS (see below)
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// must also be set to 1. If you are using the PLL, then this value must be
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// set to 0.
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//
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#define CFG_RCC_PWRDN 0
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// <q> BYPASS: PLL Bypass
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// <i> Check this box to not use the PLL for the System Clock
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//
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// Set the following value to 1 to bypass the PLL and not use it for the
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// system clock. You must set this to 1 if PWRDN (above) is set to 1. Set
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// this to 0 if you are using the PLL.
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//
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#define CFG_RCC_BYPASS 0
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// <o> XTAL: Crystal Value
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// < 0=> 0: 1.0000 MHz (can not be used with PLL)
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// < 1=> 1: 1.8432 MHz (can not be used with PLL)
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// < 2=> 2: 2.0000 MHz (can not be used with PLL)
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// < 3=> 3: 2.4576 MHz (can not be used with PLL)
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// < 4=> 4: 3.579545 MHz
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// < 5=> 5: 3.6864 MHz
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// < 6=> 6: 4.0000 MHz
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// < 7=> 7: 4.096 MHz
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// < 8=> 8: 4.9152 MHz
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// < 9=> 9: 5.0000 MHz
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// <10=> 10: 5.12 MHz
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// <11=> 11: 6.0000 MHz (default)
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// <12=> 12: 6.144 MHz
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// <13=> 13: 7.3728 MHz
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// <14=> 14: 8.0000 MHz
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// <15=> 15: 8.192 MHz
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// <i> This is the crystal frequency used for the main oscillator
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//
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// This value defines the crystal frequency for the main oscillator, according
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// to the table in the comments above. If an external crystal is used, then
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// this value must be set to match the value of the crystal.
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//
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#define CFG_RCC_XTAL 11
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// <o> OSCSRC: Oscillator Source
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// <0=> 0: MOSC Main oscillator
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// <1=> 1: IOSC Internal oscillator (default)
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// <2=> 2: IOSC/4 Internal oscillator / 4 (this is necessary
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// if used as input to PLL)
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// <3=> 3: 30kHz 30-KHz internal oscillator
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// <i> Chooses the oscillator that is used for the system clock,
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// <i> or the PLL input.
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//
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// The following value chooses the oscillator source according to the table in
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// the comments above.
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//
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#define CFG_RCC_OSCSRC 0
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// <q> IOSCDIS: Internal Oscillator Disable
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// <i> Check this box to turn off the internal oscillator
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//
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// Set the following value to 1 to turn off the internal oscillator. This
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// value can be set to 1 if you are not using the internal oscillator.
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//
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#define CFG_RCC_IOSCDIS 1
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// <q> MOSCDIS: Main Oscillator Disable
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// <i> Check this box to turn off the main oscillator
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//
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// Set the following value to 1 to turn off the main oscillator. This
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// value can be set to 1 if you are not using the main oscillator.
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//
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#define CFG_RCC_MOSCDIS 0
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// </h>
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//********************************* RCC2 *************************************
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//
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// <h> Run-Mode Clock Configuration 2 (RCC2)
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// <q> USERCC2: Use RCC2
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// <i> Check this box to override some fields in RCC. RCC2 provides
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// <i> more bits for the system clock divider, and provides an
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// <i> additional oscillator source. If you do not need these
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// <i> additional features, then leave this box unchecked.
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//
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// Set the following value to 1 to use the RCC2 register. The RCC2 register
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// overrides some of the fields in the RCC register if it is used.
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//
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#define CFG_RCC2_USERCC2 0
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// <o> SYSDIV2: System Clock Divisor <2-64>
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// <i> Specifies the divisor used to generate the system clock from
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// <i> either the PLL output of 200 MHz, or the oscillator.
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//
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// The following value is the system clock divisor. This will be applied if
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// USESYSDIV in RCC is enabled. The valid range of dividers is 2-64.
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//
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#define CFG_RCC_SYSDIV2 2
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// <q> PWRDN2: Power Down PLL
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// <i> Check this box to disable the PLL. You must also choose
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// <i> PLL Bypass.
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//
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// If the following value is 1, then the PLL is powered down. Keep this value
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// as 1 if you do not need to use the PLL. In this case, BYPASS2 (see below)
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// must also be set to 1. If you are using the PLL, then this value must be
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// set to 0.
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//
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#define CFG_RCC_PWRDN2 1
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// <q> BYPASS2: Bypass PLL
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// <i> Check this box to not use the PLL for the System Clock
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//
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// Set the following value to 1 to bypass the PLL and not use it for the
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// system clock. You must set this to 1 if PWRDN2 (above) is set to 1. Set
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// this to 0 if you are using the PLL.
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//
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#define CFG_RCC_BYPASS2 1
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// <o> OSCSRC2: Oscillator Source
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// <0=> 0: MOSC Main oscillator
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// <1=> 1: IOSC Internal oscillator (default)
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// <2=> 2: IOSC/4 Internal oscillator / 4 (this is necessary
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// if used as input to PLL)
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// <3=> 3: 30kHz 30-kHz internal oscillator
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// <7=> 7: 32kHz 32.768-kHz external oscillator
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// <i> The oscillator that is used for the system clock, or the PLL
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// input.
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//
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// The following value chooses the oscillator source according to the table in
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// the comments above.
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//
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#define CFG_RCC_OSCSRC2 1
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// </h>
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//
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// </e>
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//-------- <<< end of configuration section >>> ------------------------------
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//
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// The following macros are used to program the RCC and RCC2 registers in
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// the SystemInit() function. Edit the macros above to change these values.
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//
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#define RCC_Val \
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( \
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((CFG_RCC_SYSDIV - 1) << 23) | \
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(CFG_RCC_USESYSDIV << 22) | \
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(CFG_RCC_USEPWMDIV << 20) | \
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(CFG_RCC_PWMDIV << 17) | \
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(CFG_RCC_PWRDN << 13) | \
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(CFG_RCC_BYPASS << 11) | \
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(CFG_RCC_XTAL << 6) | \
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(CFG_RCC_OSCSRC << 4) | \
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(CFG_RCC_IOSCDIS << 1) | \
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(CFG_RCC_MOSCDIS << 1)\
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)
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#define RCC2_Val \
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( \
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(CFG_RCC2_USERCC2 << 31) | \
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((CFG_RCC_SYSDIV2 - 1) << 23) | \
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(CFG_RCC_PWRDN2 << 13) | \
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(CFG_RCC_BYPASS2 << 11) | \
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(CFG_RCC_OSCSRC2 << 4)\
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)
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//
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// The following macros are used to distinguish among various Stellaris
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// device classes and version numbers based on the SYSCTL->DID0 register.
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//
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#define CLASS_IS_SANDSTORM (((SYSCTL->DID0 & 0x70000000) == 0x00000000) || \
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((SYSCTL->DID0 & 0x70FF0000) == 0x10000000))
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#define CLASS_IS_FURY ((SYSCTL->DID0 & 0x70FF0000) == 0x10010000)
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#define CLASS_IS_DUSTDEVIL ((SYSCTL->DID0 & 0x70FF0000) == 0x10030000)
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#define CLASS_IS_TEMPEST ((SYSCTL->DID0 & 0x70FF0000) == 0x10040000)
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#define REVISION_IS_A0 ((SYSCTL->DID0 & 0x0000FFFF) == 0x00000000)
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#define REVISION_IS_A1 ((SYSCTL->DID0 & 0x0000FFFF) == 0x00000001)
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#define REVISION_IS_A2 ((SYSCTL->DID0 & 0x0000FFFF) == 0x00000002)
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#define REVISION_IS_B0 ((SYSCTL->DID0 & 0x0000FFFF) == 0x00000100)
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#define REVISION_IS_B1 ((SYSCTL->DID0 & 0x0000FFFF) == 0x00000101)
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#define REVISION_IS_C1 ((SYSCTL->DID0 & 0x0000FFFF) == 0x00000201)
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#define REVISION_IS_C2 ((SYSCTL->DID0 & 0x0000FFFF) == 0x00000202)
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#endif
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