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554 lines
18 KiB
Objective-C
554 lines
18 KiB
Objective-C
/* ============================================================================
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* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2008
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*
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* Use of this software is controlled by the terms and conditions found in the
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* license agreement under which this software has been supplied.
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* ============================================================================
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*/
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/** @file csl_mem.h
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*
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* @brief MEMORY functional layer API header file
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*
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* Path: \(CSLPATH)\ inc
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*/
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/* ============================================================================
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* Revision History
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* ================
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* 04-May-2009 Created for retention mode support on C5505 PG1.4
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* 26-May-2009 Code modified as per the review comments
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* 14-Dec-2009 Added support for partial retention mode for chip C5515
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* ============================================================================
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*/
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/** @defgroup CSL_MEM_API MEMORY
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*
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* @section Introduction
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*
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* @subsection xxx Overview
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* VC5505 DSP is having two types of internal random access memories:
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* Single Access RAM(SARAM) and Dual Access RAM(DARAM).
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* C5505 features 32Kx16-bit of DARAM. The DARAM is composed of 8 blocks of
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* 4Kx16- bit each. The DARAM is located in the byte address
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* range 0000h-0FFFFh. It can be accessed by program, data and DMA busses.
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* C5505 features 128Kx16-bit of on-chip SARAM. The SARAM is composed of 32
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* blocks of 4Kx16-bit each. The SARAM is located in the byte address range
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* 010000h-04FFFFh. It can be accessed by the program, data and DMA busses.
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*
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* CSL MEMORY module can be used to enable or disable the memory retention
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* mode for SARAM and DARAM. With memory retention enabled memory goes to
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* low power mode while maintaining its contents. When the memory is placed
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* in retention mode no accesses is allowed. Accessing the data after enabling
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* memory retention mode will result in data corruption. DARAM or SARAM can be
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* independently configured for the memory retention mode. Enabling partial
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* memory retention mode for SARAM or DARAM is not possible.
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*
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* @subsection References
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* C5505_Spec_1.16.pdf
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*/
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#ifndef _CSL_MEM_H_
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#define _CSL_MEM_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <cslr.h>
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#include <csl_error.h>
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#include <csl_types.h>
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#include <soc.h>
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#include <csl_general.h>
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/**
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@defgroup CSL_MEM_SYMBOL MEMORY Symbols Defined
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@ingroup CSL_MEM_API
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*/
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/**
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@defgroup CSL_MEM_DATASTRUCT MEMORY Data Structures
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@ingroup CSL_MEM_API
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*/
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/**
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@defgroup CSL_MEM_FUNCTION MEMORY Functions
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@ingroup CSL_MEM_API
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*/
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/**
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@defgroup CSL_MEM_ENUM MEMORY Enumerated Data Types
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@ingroup CSL_MEM_API
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*/
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/*****************************************************************************\
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MEMORY global macro declarations
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\*****************************************************************************/
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/** @addtogroup CSL_MEM_SYMBOL
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@{ */
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/** Number of banks in DARAM memory */
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#define CSL_DARAM_BANK_COUNT (8)
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/** Number of banks in SARAM memory */
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#define CSL_SARAM_BANK_COUNT (32)
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/** Maximum allowed bank number for DARAM memory */
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#define CSL_DARAM_BANK_NUM_MAX (CSL_DARAM_BANK_COUNT - 1)
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/** Maximum allowed bank number for SARAM memory */
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#define CSL_SARAM_BANK_NUM_MAX (CSL_SARAM_BANK_COUNT - 1)
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/** Macro to indicate DARAM Bank 0 */
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#define CSL_MEM_DARAM_BANK0 (0)
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/** Macro to indicate DARAM Bank 7 */
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#define CSL_MEM_DARAM_BANK7 (7u)
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/** Macro to indicate SARAM Bank 0 */
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#define CSL_MEM_SARAM_BANK0 (0)
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/** Macro to indicate SARAM Bank 8 */
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#define CSL_MEM_SARAM_BANK8 (8u)
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/** Macro to indicate SARAM Bank 16 */
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#define CSL_MEM_SARAM_BANK16 (16u)
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/** Macro to indicate SARAM Bank 24 */
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#define CSL_MEM_SARAM_BANK24 (24u)
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/** Macro to indicate SARAM Bank 31 */
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#define CSL_MEM_SARAM_BANK31 (31u)
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/** Macro value to enable to memory retention mode for all the blocks */
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#define CSL_MEM_ENABLE_ALL_SLEEP (0xAAAAu)
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/** Macro value to disable to memory retention mode for all the blocks */
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#define CSL_MEM_DISABLE_ALL_SLEEP (0xFFFFu)
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/** Macro value to enable to memory retention mode for single bank */
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#define CSL_MEM_ENABLE_BANK_SLEEP (0x0002)
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/** Macro value to disable to memory retention mode for single bank */
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#define CSL_MEM_DISABLE_BANK_SLEEP (0x0003)
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/** Mask for sleep mode control register bits of a memory bank */
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#define CSL_MEM_SLEEPMODE_BIT_MASK (0x0003)
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/** Maximum value of bank mask for DARAM memory */
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#define CSL_MEM_DARAM_BANKMASK (0xFFu)
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/** Macro to make the bank mask based on the bank number */
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#define CSL_MEM_MAKE_BANKMASK(bankNumber) ((Uint32)1 << bankNumber)
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/**
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@} */
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/**************************************************************************\
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* MEMORY global typedef declarations *
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\**************************************************************************/
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/** @addtogroup CSL_MEM_ENUM
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@{ */
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/**
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* \brief
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*
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* This enum holds the values to represent the type of the CPU memory.
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* Application program can send a request to a specific memory
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* using this enum.
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*/
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typedef enum
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{
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CSL_MEM_DARAM, /* Memory type is DARAM */
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CSL_MEM_SARAM, /* Memory type is SARAM */
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CSL_MEM_INVALID /* Invalid Memory type */
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} CSL_MemType;
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/**
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* \brief
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*
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* This enum holds the values to switch the mSDRAM output clock state
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*/
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typedef enum
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{
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CSL_MEM_MSDARAM_CLOCK_ON, /* MSDARAM clock will be set to ON */
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CSL_MEM_MSDARAM_CLOCK_OFF /* MSDARAM clock will be set to OFF */
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} CSL_MEMmSDRAMClock;
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/**
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@} */
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/**************************************************************************\
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* MEMORY function declarations *
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\**************************************************************************/
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/** @addtogroup CSL_MEM_FUNCTION
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@{ */
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/** ===========================================================================
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* @n@b MEM_init
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*
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* @b Description
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* @n This is the initialization function for the memory CSL module.
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* No functionality is added for this API. This function always returns
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* success. This function is provided for the future use.
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*
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* @b Arguments
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* @verbatim
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None
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@endverbatim
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*
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* <b> Return Value </b>
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* @li CSL_SOK
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*
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* <b> Pre Condition </b>
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* @n None
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*
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* <b> Post Condition </b>
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* @n None
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*
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* @b Modifies
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* @n None
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*
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* @b Example
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* @verbatim
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CSL_Status status;
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status = MEM_init();
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@endverbatim
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* ===========================================================================
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*/
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CSL_Status MEM_init(void);
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/** ===========================================================================
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* @n@b MEM_enableRetentionMode
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*
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* @b Description
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* @n This function enables the retention mode for whole DARAM or SARAM.
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* In the memory retention mode memory goes to low power mode while
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* maintaining its contents. When the memory is placed in retention mode,
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* no accesses is allowed. Memory retention mode is enabled by
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* configuring the RAM Sleep Mode Control Register.
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* DARAM or SARAM can be independently configured for the memory
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* retention mode using this API.
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*
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* NOTE: This function enables memory retention mode for the entire
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* DARAM or SARAM. This function can be used on both chips C5505
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* and C5515.
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*
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* @verbatim
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memType Type of the CPU memory - DARAM/SARAM
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@endverbatim
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*
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* <b> Return Value </b>
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* @li CSL_SOK - Returned for success
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* @li CSL_ESYS_INVPARAMS - Invalid input parameters
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*
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* <b> Pre Condition </b>
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* @n None
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*
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* <b> Post Condition </b>
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* @n Enables memory retention mode for the memory specified
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*
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* @b Modifies
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* @n RAM Sleep Mode Control Register
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*
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* @b Example
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* @verbatim
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CSL_Status status;
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status = MEM_enableRetentionMode (CSL_MEM_DARAM);
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@endverbatim
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* ===========================================================================
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*/
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CSL_Status MEM_enableRetentionMode (CSL_MemType memType);
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/** ===========================================================================
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* @n@b MEM_disableRetentionMode
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*
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* @b Description
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* @n This function disables the memory retention mode for DARAM or SARAM.
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* Memory retention mode is disabled by configuring the RAM Sleep Mode
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* Control Register.
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* Memory retention mode for DARAM or SARAM can be independently
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* disabled using this API.
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*
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* NOTE: This function disables memory retention mode for the entire
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* DARAM or SARAM. This function can be used on both chips C5505
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* and C5515.
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*
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* @verbatim
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memType Type of the CPU memory - DARAM/SARAM
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@endverbatim
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*
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* <b> Return Value </b>
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* @li CSL_SOK - Returned for success
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* @li CSL_ESYS_INVPARAMS - Invalid input parameters
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*
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* <b> Pre Condition </b>
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* @n None
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*
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* <b> Post Condition </b>
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* @n Disables memory retention mode for the memory specified
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*
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* @b Modifies
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* @n RAM Sleep Mode Control Register
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*
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* @b Example
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* @verbatim
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CSL_Status status;
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status = MEM_disableRetentionMode (CSL_MEM_DARAM);
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@endverbatim
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* ===========================================================================
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*/
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CSL_Status MEM_disableRetentionMode (CSL_MemType memType);
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#if (defined(CHIP_C5505_C5515) || defined(CHIP_C5504_C5514))
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/** ===========================================================================
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* @n@b MEM_enablePartialRetentionMode
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*
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* @b Description
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* @n This function enables retention mode for single or group of banks
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* in DARAM or SARAM. In the memory retention mode memory goes to low
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* power mode while maintaining its contents. When the memory is placed
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* in retention mode, no accesses is allowed. Memory retention mode is
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* enabled by configuring the RAM Sleep Mode Control Register.
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* Any memory bank of DARAM or SARAM can be independently configured
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* for the memory retention mode using this API. Enabling memory retention
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* mode for a particular bank will effect that memory bank only and rest
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* of the memory works normally.
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*
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*
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* Usage of parameters 'bankNumber' and 'bankMask'
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* This API provides two parameters to select a single block of memory
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* or a group of memory banks to enable retention mode
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*
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* bankNumber: Used to select a single block of memory. This number will
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* be from 0 to 7 for DARAM and 0 to 31 for SARAM. This input is provided
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* for to make bank number selection easy.
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*
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* bankMask: This is a 32 bit number each bit represents one memory bank.
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* For DARAM only 8 bits are valid. To enable memory retention mode for a
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* memory bank set corresponding bit of 'bankMask' to '1'. For example
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* to enable memory retention mode for SARAM banks 0, 5 and 12, value of
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* 'bankMask' should be 0x1021. Use the macro CSL_MEM_MAKE_BANKMASK to
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* make the bankMask.
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*
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* Set 'bankMask' to '0' while using 'bankNumber' for selecting a single
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* bank. Set 'bankNumber' to '0' while using 'bankMask' for selecting
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* a group of banks.
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*
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* NOTE: PARTIAL MEMORY RETENTION MODE IS NOT SUPPORTED ON THE CHIP C5505
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*
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* @verbatim
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memType Type of the CPU memory - DARAM/SARAM
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bankNumber Bank number - To select a single memory bank.
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bankMask Bank mask - To select a group of memory banks.
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@endverbatim
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*
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* <b> Return Value </b>
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* @li CSL_SOK - Returned for success
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* @li CSL_ESYS_INVPARAMS - Invalid input parameters
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*
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* <b> Pre Condition </b>
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* @n None
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*
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* <b> Post Condition </b>
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* @n Enables memory retention mode for the memory specified
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*
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* @b Modifies
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* @n RAM Sleep Mode Control Register
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*
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* @b Example
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* @verbatim
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CSL_Status status;
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Uint32 bankMask;
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bankMask = 0
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//Enable memory retention mode for SARAM bank 5
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status = MEM_enablePartialRetentionMode (CSL_MEM_SARAM, 5, 0);
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//Enable memory retention mode for SARAM banks 6, 25, 30.
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bankMask = CSL_MEM_MAKE_BANKMASK(6);
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bankMask |= CSL_MEM_MAKE_BANKMASK(25);
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bankMask |= CSL_MEM_MAKE_BANKMASK(30);
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status = MEM_enablePartialRetentionMode (CSL_MEM_SARAM, 0,
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bankMask);
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@endverbatim
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* ===========================================================================
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*/
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CSL_Status MEM_enablePartialRetentionMode (CSL_MemType memType,
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Uint16 bankNumber,
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Uint32 bankMask);
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/** ===========================================================================
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* @n@b MEM_disablePartialRetentionMode
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*
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* @b Description
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* @n This function disables retention mode for single or group of banks
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* in DARAM or SARAM. Memory retention mode is disabled by configuring
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* the RAM Sleep Mode Control Register.
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* Any memory bank of DARAM or SARAM can be independently configured
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* for disabling memory retention mode using this API.
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*
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*
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* Usage of parameters 'bankNumber' and 'bankMask'
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* This API provides two parameters to select a single block of memory
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* or a group of memory banks to disable retention mode
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*
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* bankNumber: Used to select a single block of memory. This number will
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* be from 0 to 7 for DARAM and 0 to 31 for SARAM. This input is provided
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* for to make bank number selection easy.
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*
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* bankMask: This is a 32 bit number each bit represents one memory bank.
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* For DARAM only 8 bits are valid. To disable memory retention mode for a
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* memory bank set corresponding bit of 'bankMask' to '1'. For example
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* to disable memory retention mode for SARAM banks 0, 5 and 12, value of
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* 'bankMask' should be 0x1021. Use the macro CSL_MEM_MAKE_BANKMASK to
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* make the bankMask.
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*
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* Set 'bankMask' to '0' while using 'bankNumber' for selecting a single
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* bank. Set 'bankNumber' to '0' while using 'bankMask' for selecting
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* a group of banks.
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*
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* NOTE: PARTIAL MEMORY RETENTION MODE IS NOT SUPPORTED ON THE CHIP C5505
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*
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* @verbatim
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memType Type of the CPU memory - DARAM/SARAM
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bankNumber Bank number - To select a single memory bank.
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bankMask Bank mask - To select a group of memory banks.
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@end verbatim
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*
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* <b> Return Value </b>
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* @li CSL_SOK - Returned for success
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* @li CSL_ESYS_INVPARAMS - Invalid input parameters
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*
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* <b> Pre Condition </b>
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* @n None
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*
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* <b> Post Condition </b>
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* @n Disables memory retention mode for the memory specified
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*
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* @b Modifies
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* @n RAM Sleep Mode Control Register
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*
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* @b Example
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* @verbatim
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CSL_Status status;
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Uint32 bankMask;
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bankMask = 0
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//Disable memory retention mode for SARAM bank 5
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status = MEM_disablePartialRetentionMode (CSL_MEM_SARAM, 5, 0);
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//Disable memory retention mode for SARAM banks 6, 25, 30.
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bankMask = CSL_MEM_MAKE_BANKMASK(6);
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bankMask |= CSL_MEM_MAKE_BANKMASK(25);
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bankMask |= CSL_MEM_MAKE_BANKMASK(30);
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status = MEM_disablePartialRetentionMode (CSL_MEM_SARAM, 0,
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bankMask);
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@endverbatim
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* ===========================================================================
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*/
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CSL_Status MEM_disablePartialRetentionMode (CSL_MemType memType,
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Uint16 bankNum,
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Uint32 bankMask);
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/** ===========================================================================
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* @n@b MEM_setmSDRAMClock
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*
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* @b Description
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* @n This function is used to make the mSDRAM Clock output switch ON and OFF
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*
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* @verbatim
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clockSwitch Value to switch the clock
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@end verbatim
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*
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* <b> Return Value </b>
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* @li CSL_SOK - Returned for success
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* @li CSL_ESYS_INVPARAMS - Invalid input parameters
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*
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* <b> Pre Condition </b>
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* @n None
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*
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* <b> Post Condition </b>
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* @n Configures the mSDRAM output clock state
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*
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* @b Modifies
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* @n SDRAM clock control register
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*
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* @b Example
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* @verbatim
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CSL_Status status;
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// Turn the mSDRAM output clock ON
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status = MEM_setmSDRAMClock (CSL_MEM_MSDARAM_CLOCK_ON);
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@endverbatim
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* ===========================================================================
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*/
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CSL_Status MEM_setmSDRAMClock (CSL_MEMmSDRAMClock clockSwitch);
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/** ===========================================================================
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* @n@b MEM_getmSDRAMClock
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*
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* @b Description
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* @n This function is used to get the value mSDRAM Clock output switch.
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*
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* @verbatim
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None
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@end verbatim
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*
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* <b> Return Value </b> Bool
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* @li TRUE - mSDRAM Clock output switch is OFF
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* @li FALSE - mSDRAM Clock output switch ON
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*
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* <b> Pre Condition </b>
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* @n None
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*
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* <b> Post Condition </b>
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* @n None
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*
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* @b Modifies
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* @n None
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*
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* @b Example
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* @verbatim
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Bool clkStatus;
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clkStatus = MEM_getmSDRAMClock();
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@endverbatim
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* ===========================================================================
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*/
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Bool MEM_getmSDRAMClock (void);
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#endif
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/**
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@} */
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#ifdef __cplusplus
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}
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#endif
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#endif // _CSL_MEM_H_
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