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542 lines
18 KiB
C
542 lines
18 KiB
C
/********************************************************************
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* Copyright (C) 2003-2008 Texas Instruments Incorporated.
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* All Rights Reserved
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*********************************************************************
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* file: cslr_dma.h
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*
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* Brief: This file contains the Register Description for dma
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*
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*********************************************************************/
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#ifndef _CSLR_DMA_H_
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#define _CSLR_DMA_H_
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#include <cslr.h>
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#include <tistdtypes.h>
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#include <csl_general.h>
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/* Minimum unit = 2 bytes */
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/**************************************************************************\
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* Register Overlay Structure
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\**************************************************************************/
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typedef struct {
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volatile Uint16 DMACH0SSAL;
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volatile Uint16 DMACH0SSAU;
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volatile Uint16 DMACH0DSAL;
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volatile Uint16 DMACH0DSAU;
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volatile Uint16 DMACH0TCR1;
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volatile Uint16 DMACH0TCR2;
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volatile Uint16 RSVD0[26];
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volatile Uint16 DMACH1SSAL;
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volatile Uint16 DMACH1SSAU;
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volatile Uint16 DMACH1DSAL;
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volatile Uint16 DMACH1DSAU;
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volatile Uint16 DMACH1TCR1;
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volatile Uint16 DMACH1TCR2;
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volatile Uint16 RSVD1[26];
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volatile Uint16 DMACH2SSAL;
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volatile Uint16 DMACH2SSAU;
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volatile Uint16 DMACH2DSAL;
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volatile Uint16 DMACH2DSAU;
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volatile Uint16 DMACH2TCR1;
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volatile Uint16 DMACH2TCR2;
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volatile Uint16 RSVD2[26];
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volatile Uint16 DMACH3SSAL;
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volatile Uint16 DMACH3SSAU;
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volatile Uint16 DMACH3DSAL;
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volatile Uint16 DMACH3DSAU;
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volatile Uint16 DMACH3TCR1;
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volatile Uint16 DMACH3TCR2;
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} CSL_DmaRegs;
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/**************************************************************************\
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* Field Definition Macros
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\**************************************************************************/
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/* DMACH0SSAL */
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#define CSL_DMA_DMACH0SSAL_SSAL_MASK (0xFFFFu)
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#define CSL_DMA_DMACH0SSAL_SSAL_SHIFT (0x0000u)
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#define CSL_DMA_DMACH0SSAL_SSAL_RESETVAL (0x0000u)
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#define CSL_DMA_DMACH0SSAL_RESETVAL (0x0000u)
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/* DMACH0SSAU */
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#define CSL_DMA_DMACH0SSAU_SSAU_MASK (0xFFFFu)
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#define CSL_DMA_DMACH0SSAU_SSAU_SHIFT (0x0000u)
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#define CSL_DMA_DMACH0SSAU_SSAU_RESETVAL (0x0000u)
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#define CSL_DMA_DMACH0SSAU_RESETVAL (0x0000u)
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/* DMACH0DSAL */
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#define CSL_DMA_DMACH0DSAL_DSAL_MASK (0xFFFFu)
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#define CSL_DMA_DMACH0DSAL_DSAL_SHIFT (0x0000u)
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#define CSL_DMA_DMACH0DSAL_DSAL_RESETVAL (0x0000u)
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#define CSL_DMA_DMACH0DSAL_RESETVAL (0x0000u)
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/* DMACH0DSAU */
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#define CSL_DMA_DMACH0DSAU_DSAU_MASK (0xFFFFu)
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#define CSL_DMA_DMACH0DSAU_DSAU_SHIFT (0x0000u)
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#define CSL_DMA_DMACH0DSAU_DSAU_RESETVAL (0x0000u)
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#define CSL_DMA_DMACH0DSAU_RESETVAL (0x0000u)
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/* DMACH0TCR1 */
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#define CSL_DMA_DMACH0TCR1_LENGTH_MASK (0xFFFFu)
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#define CSL_DMA_DMACH0TCR1_LENGTH_SHIFT (0x0000u)
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#define CSL_DMA_DMACH0TCR1_LENGTH_RESETVAL (0x0000u)
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#define CSL_DMA_DMACH0TCR1_RESETVAL (0x0000u)
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/* DMACH0TCR2 */
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#define CSL_DMA_DMACH0TCR2_EN_MASK (0x8000u)
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#define CSL_DMA_DMACH0TCR2_EN_SHIFT (0x000Fu)
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#define CSL_DMA_DMACH0TCR2_EN_RESETVAL (0x0000u)
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/*----EN Tokens----*/
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#define CSL_DMA_DMACH0TCR2_EN_ENABLE (0x0000u)
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#define CSL_DMA_DMACH0TCR2_EN_DISABLE (0x0001u)
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#define CSL_DMA_DMACH0TCR2_STATUS_MASK (0x4000u)
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#define CSL_DMA_DMACH0TCR2_STATUS_SHIFT (0x000Eu)
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#define CSL_DMA_DMACH0TCR2_STATUS_RESETVAL (0x0000u)
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/*----STATUS Tokens----*/
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#define CSL_DMA_DMACH0TCR2_STATUS_DONE (0x0000u)
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#define CSL_DMA_DMACH0TCR2_STATUS_ACTIVE (0x0001u)
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#define CSL_DMA_DMACH0TCR2_INTEN_MASK (0x2000u)
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#define CSL_DMA_DMACH0TCR2_INTEN_SHIFT (0x000Du)
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#define CSL_DMA_DMACH0TCR2_INTEN_RESETVAL (0x0000u)
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/*----INTEN Tokens----*/
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#define CSL_DMA_DMACH0TCR2_INTEN_DISABLE (0x0000u)
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#define CSL_DMA_DMACH0TCR2_INTEN_ENABLE (0x0001u)
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#define CSL_DMA_DMACH0TCR2_AUTORLD_MASK (0x1000u)
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#define CSL_DMA_DMACH0TCR2_AUTORLD_SHIFT (0x000Cu)
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#define CSL_DMA_DMACH0TCR2_AUTORLD_RESETVAL (0x0000u)
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/*----AUTORLD Tokens----*/
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#define CSL_DMA_DMACH0TCR2_AUTORLD_DISABLE (0x0000u)
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#define CSL_DMA_DMACH0TCR2_AUTORLD_ENABLE (0x0001u)
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#define CSL_DMA_DMACH0TCR2_DSTAMODE_MASK (0x0300u)
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#define CSL_DMA_DMACH0TCR2_DSTAMODE_SHIFT (0x0008u)
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#define CSL_DMA_DMACH0TCR2_DSTAMODE_RESETVAL (0x0000u)
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/*----DSTAMODE Tokens----*/
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#define CSL_DMA_DMACH0TCR2_DSTAMODE_INCR (0x0000u)
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#define CSL_DMA_DMACH0TCR2_DSTAMODE_RSV1 (0x0001u)
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#define CSL_DMA_DMACH0TCR2_DSTAMODE_CONST (0x0002u)
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#define CSL_DMA_DMACH0TCR2_DSTAMODE_RSV3 (0x0003u)
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#define CSL_DMA_DMACH0TCR2_SRCAMODE_MASK (0x00C0u)
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#define CSL_DMA_DMACH0TCR2_SRCAMODE_SHIFT (0x0006u)
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#define CSL_DMA_DMACH0TCR2_SRCAMODE_RESETVAL (0x0000u)
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/*----SRCAMODE Tokens----*/
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#define CSL_DMA_DMACH0TCR2_SRCAMODE_INCR (0x0000u)
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#define CSL_DMA_DMACH0TCR2_SRCAMODE_RSV1 (0x0001u)
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#define CSL_DMA_DMACH0TCR2_SRCAMODE_CONST (0x0002u)
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#define CSL_DMA_DMACH0TCR2_SRCAMODE_RSV3 (0x0003u)
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#define CSL_DMA_DMACH0TCR2_BURSTMODE_MASK (0x0038u)
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#define CSL_DMA_DMACH0TCR2_BURSTMODE_SHIFT (0x0003u)
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#define CSL_DMA_DMACH0TCR2_BURSTMODE_RESETVAL (0x0000u)
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#define CSL_DMA_DMACH0TCR2_SYNCMODE_MASK (0x0004u)
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#define CSL_DMA_DMACH0TCR2_SYNCMODE_SHIFT (0x0002u)
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#define CSL_DMA_DMACH0TCR2_SYNCMODE_RESETVAL (0x0000u)
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/*----SYNCMODE Tokens----*/
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#define CSL_DMA_DMACH0TCR2_SYNCMODE_NOSYNC (0x0000u)
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#define CSL_DMA_DMACH0TCR2_SYNCMODE_SYNC (0x0001u)
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#if (defined(CHIP_C5505_C5515) || defined(CHIP_C5504_C5514))
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#define CSL_DMA_DMACH0TCR2_LTSTATUS_MASK (0x0002u)
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#define CSL_DMA_DMACH0TCR2_LTSTATUS_SHIFT (0x0001u)
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#define CSL_DMA_DMACH0TCR2_LTSTATUS_RESETVAL (0x0000u)
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#define CSL_DMA_DMACH0TCR2_EPPMODE_MASK (0x0001u)
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#define CSL_DMA_DMACH0TCR2_EPPMODE_SHIFT (0x0000u)
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#define CSL_DMA_DMACH0TCR2_EPPMODE_RESETVAL (0x0000u)
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#endif
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#define CSL_DMA_DMACH0TCR2_RESETVAL (0x0000u)
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/* DMACH1SSAL */
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#define CSL_DMA_DMACH1SSAL_SSAL_MASK (0xFFFFu)
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#define CSL_DMA_DMACH1SSAL_SSAL_SHIFT (0x0000u)
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#define CSL_DMA_DMACH1SSAL_SSAL_RESETVAL (0x0000u)
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#define CSL_DMA_DMACH1SSAL_RESETVAL (0x0000u)
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/* DMACH1SSAU */
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#define CSL_DMA_DMACH1SSAU_SSAU_MASK (0xFFFFu)
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#define CSL_DMA_DMACH1SSAU_SSAU_SHIFT (0x0000u)
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#define CSL_DMA_DMACH1SSAU_SSAU_RESETVAL (0x0000u)
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#define CSL_DMA_DMACH1SSAU_RESETVAL (0x0000u)
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/* DMACH1DSAL */
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#define CSL_DMA_DMACH1DSAL_DSAL_MASK (0xFFFFu)
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#define CSL_DMA_DMACH1DSAL_DSAL_SHIFT (0x0000u)
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#define CSL_DMA_DMACH1DSAL_DSAL_RESETVAL (0x0000u)
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#define CSL_DMA_DMACH1DSAL_RESETVAL (0x0000u)
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/* DMACH1DSAU */
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#define CSL_DMA_DMACH1DSAU_DSAU_MASK (0xFFFFu)
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#define CSL_DMA_DMACH1DSAU_DSAU_SHIFT (0x0000u)
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#define CSL_DMA_DMACH1DSAU_DSAU_RESETVAL (0x0000u)
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#define CSL_DMA_DMACH1DSAU_RESETVAL (0x0000u)
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/* DMACH1TCR1 */
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#define CSL_DMA_DMACH1TCR1_LENGTH_MASK (0xFFFFu)
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#define CSL_DMA_DMACH1TCR1_LENGTH_SHIFT (0x0000u)
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#define CSL_DMA_DMACH1TCR1_LENGTH_RESETVAL (0x0000u)
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#define CSL_DMA_DMACH1TCR1_RESETVAL (0x0000u)
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/* DMACH1TCR2 */
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#define CSL_DMA_DMACH1TCR2_EN_MASK (0x8000u)
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#define CSL_DMA_DMACH1TCR2_EN_SHIFT (0x000Fu)
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#define CSL_DMA_DMACH1TCR2_EN_RESETVAL (0x0000u)
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/*----EN Tokens----*/
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#define CSL_DMA_DMACH1TCR2_EN_ENABLE (0x0000u)
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#define CSL_DMA_DMACH1TCR2_EN_DISABLE (0x0001u)
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#define CSL_DMA_DMACH1TCR2_STATUS_MASK (0x4000u)
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#define CSL_DMA_DMACH1TCR2_STATUS_SHIFT (0x000Eu)
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#define CSL_DMA_DMACH1TCR2_STATUS_RESETVAL (0x0000u)
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/*----STATUS Tokens----*/
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#define CSL_DMA_DMACH1TCR2_STATUS_DONE (0x0000u)
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#define CSL_DMA_DMACH1TCR2_STATUS_ACTIVE (0x0001u)
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#define CSL_DMA_DMACH1TCR2_INTEN_MASK (0x2000u)
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#define CSL_DMA_DMACH1TCR2_INTEN_SHIFT (0x000Du)
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#define CSL_DMA_DMACH1TCR2_INTEN_RESETVAL (0x0000u)
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/*----INTEN Tokens----*/
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#define CSL_DMA_DMACH1TCR2_INTEN_DISABLE (0x0000u)
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#define CSL_DMA_DMACH1TCR2_INTEN_ENABLE (0x0001u)
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#define CSL_DMA_DMACH1TCR2_AUTORLD_MASK (0x1000u)
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#define CSL_DMA_DMACH1TCR2_AUTORLD_SHIFT (0x000Cu)
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#define CSL_DMA_DMACH1TCR2_AUTORLD_RESETVAL (0x0000u)
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/*----AUTORLD Tokens----*/
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#define CSL_DMA_DMACH1TCR2_AUTORLD_DISABLE (0x0000u)
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#define CSL_DMA_DMACH1TCR2_AUTORLD_ENABLE (0x0001u)
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#define CSL_DMA_DMACH1TCR2_DSTAMODE_MASK (0x0300u)
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#define CSL_DMA_DMACH1TCR2_DSTAMODE_SHIFT (0x0008u)
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#define CSL_DMA_DMACH1TCR2_DSTAMODE_RESETVAL (0x0000u)
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/*----DSTAMODE Tokens----*/
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#define CSL_DMA_DMACH1TCR2_DSTAMODE_INCR (0x0000u)
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#define CSL_DMA_DMACH1TCR2_DSTAMODE_RSV1 (0x0001u)
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#define CSL_DMA_DMACH1TCR2_DSTAMODE_CONST (0x0002u)
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#define CSL_DMA_DMACH1TCR2_DSTAMODE_RSV3 (0x0003u)
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#define CSL_DMA_DMACH1TCR2_SRCAMODE_MASK (0x00C0u)
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#define CSL_DMA_DMACH1TCR2_SRCAMODE_SHIFT (0x0006u)
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#define CSL_DMA_DMACH1TCR2_SRCAMODE_RESETVAL (0x0000u)
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/*----SRCAMODE Tokens----*/
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#define CSL_DMA_DMACH1TCR2_SRCAMODE_INCR (0x0000u)
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#define CSL_DMA_DMACH1TCR2_SRCAMODE_RSV1 (0x0001u)
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#define CSL_DMA_DMACH1TCR2_SRCAMODE_CONST (0x0002u)
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#define CSL_DMA_DMACH1TCR2_SRCAMODE_RSV3 (0x0003u)
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#define CSL_DMA_DMACH1TCR2_BURSTMODE_MASK (0x0038u)
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#define CSL_DMA_DMACH1TCR2_BURSTMODE_SHIFT (0x0003u)
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#define CSL_DMA_DMACH1TCR2_BURSTMODE_RESETVAL (0x0000u)
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/*----BURSTMODE Tokens----*/
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#define CSL_DMA_DMACH1TCR2_BURSTMODE_1DWORD (0x0000u)
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#define CSL_DMA_DMACH1TCR2_BURSTMODE_2DWORDS (0x0001u)
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#define CSL_DMA_DMACH1TCR2_BURSTMODE_4DWORDS (0x0002u)
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#define CSL_DMA_DMACH1TCR2_BURSTMODE_8DWORDS (0x0003u)
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#define CSL_DMA_DMACH1TCR2_BURSTMODE_16DWORDS (0x0004u)
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#define CSL_DMA_DMACH1TCR2_BURSTMODE_RSV5 (0x0005u)
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#define CSL_DMA_DMACH1TCR2_BURSTMODE_RSV6 (0x0006u)
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#define CSL_DMA_DMACH1TCR2_BURSTMODE_RSV7 (0x0007u)
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#define CSL_DMA_DMACH1TCR2_SYNCMODE_MASK (0x0004u)
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#define CSL_DMA_DMACH1TCR2_SYNCMODE_SHIFT (0x0002u)
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#define CSL_DMA_DMACH1TCR2_SYNCMODE_RESETVAL (0x0000u)
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/*----SYNCMODE Tokens----*/
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#define CSL_DMA_DMACH1TCR2_SYNCMODE_NOSYNC (0x0000u)
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#define CSL_DMA_DMACH1TCR2_SYNCMODE_SYNC (0x0001u)
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#if (defined(CHIP_C5505_C5515) || defined(CHIP_C5504_C5514))
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#define CSL_DMA_DMACH1TCR2_LTSTATUS_MASK (0x0002u)
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#define CSL_DMA_DMACH1TCR2_LTSTATUS_SHIFT (0x0001u)
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#define CSL_DMA_DMACH1TCR2_LTSTATUS_RESETVAL (0x0000u)
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#define CSL_DMA_DMACH1TCR2_EPPMODE_MASK (0x0001u)
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#define CSL_DMA_DMACH1TCR2_EPPMODE_SHIFT (0x0000u)
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#define CSL_DMA_DMACH1TCR2_EPPMODE_RESETVAL (0x0000u)
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#endif
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#define CSL_DMA_DMACH1TCR2_RESETVAL (0x0000u)
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/* DMACH2SSAL */
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#define CSL_DMA_DMACH2SSAL_SSAL_MASK (0xFFFFu)
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#define CSL_DMA_DMACH2SSAL_SSAL_SHIFT (0x0000u)
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#define CSL_DMA_DMACH2SSAL_SSAL_RESETVAL (0x0000u)
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#define CSL_DMA_DMACH2SSAL_RESETVAL (0x0000u)
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/* DMACH2SSAU */
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#define CSL_DMA_DMACH2SSAU_SSAU_MASK (0xFFFFu)
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#define CSL_DMA_DMACH2SSAU_SSAU_SHIFT (0x0000u)
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#define CSL_DMA_DMACH2SSAU_SSAU_RESETVAL (0x0000u)
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#define CSL_DMA_DMACH2SSAU_RESETVAL (0x0000u)
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/* DMACH2DSAL */
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#define CSL_DMA_DMACH2DSAL_DSAL_MASK (0xFFFFu)
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#define CSL_DMA_DMACH2DSAL_DSAL_SHIFT (0x0000u)
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#define CSL_DMA_DMACH2DSAL_DSAL_RESETVAL (0x0000u)
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#define CSL_DMA_DMACH2DSAL_RESETVAL (0x0000u)
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/* DMACH2DSAU */
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#define CSL_DMA_DMACH2DSAU_DSAU_MASK (0xFFFFu)
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#define CSL_DMA_DMACH2DSAU_DSAU_SHIFT (0x0000u)
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#define CSL_DMA_DMACH2DSAU_DSAU_RESETVAL (0x0000u)
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#define CSL_DMA_DMACH2DSAU_RESETVAL (0x0000u)
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/* DMACH2TCR1 */
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#define CSL_DMA_DMACH2TCR1_LENGTH_MASK (0xFFFFu)
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#define CSL_DMA_DMACH2TCR1_LENGTH_SHIFT (0x0000u)
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#define CSL_DMA_DMACH2TCR1_LENGTH_RESETVAL (0x0000u)
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#define CSL_DMA_DMACH2TCR1_RESETVAL (0x0000u)
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/* DMACH2TCR2 */
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#define CSL_DMA_DMACH2TCR2_EN_MASK (0x8000u)
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#define CSL_DMA_DMACH2TCR2_EN_SHIFT (0x000Fu)
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#define CSL_DMA_DMACH2TCR2_EN_RESETVAL (0x0000u)
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/*----EN Tokens----*/
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#define CSL_DMA_DMACH2TCR2_EN_ENABLE (0x0000u)
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#define CSL_DMA_DMACH2TCR2_EN_DISABLE (0x0001u)
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#define CSL_DMA_DMACH2TCR2_STATUS_MASK (0x4000u)
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#define CSL_DMA_DMACH2TCR2_STATUS_SHIFT (0x000Eu)
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#define CSL_DMA_DMACH2TCR2_STATUS_RESETVAL (0x0000u)
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/*----STATUS Tokens----*/
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#define CSL_DMA_DMACH2TCR2_STATUS_DONE (0x0000u)
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#define CSL_DMA_DMACH2TCR2_STATUS_ACTIVE (0x0001u)
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#define CSL_DMA_DMACH2TCR2_INTEN_MASK (0x2000u)
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#define CSL_DMA_DMACH2TCR2_INTEN_SHIFT (0x000Du)
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#define CSL_DMA_DMACH2TCR2_INTEN_RESETVAL (0x0000u)
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/*----INTEN Tokens----*/
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#define CSL_DMA_DMACH2TCR2_INTEN_DISABLE (0x0000u)
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#define CSL_DMA_DMACH2TCR2_INTEN_ENABLE (0x0001u)
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#define CSL_DMA_DMACH2TCR2_AUTORLD_MASK (0x1000u)
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#define CSL_DMA_DMACH2TCR2_AUTORLD_SHIFT (0x000Cu)
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#define CSL_DMA_DMACH2TCR2_AUTORLD_RESETVAL (0x0000u)
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/*----AUTORLD Tokens----*/
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#define CSL_DMA_DMACH2TCR2_AUTORLD_DISABLE (0x0000u)
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#define CSL_DMA_DMACH2TCR2_AUTORLD_ENABLE (0x0001u)
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#define CSL_DMA_DMACH2TCR2_DSTAMODE_MASK (0x0300u)
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#define CSL_DMA_DMACH2TCR2_DSTAMODE_SHIFT (0x0008u)
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#define CSL_DMA_DMACH2TCR2_DSTAMODE_RESETVAL (0x0000u)
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/*----DSTAMODE Tokens----*/
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#define CSL_DMA_DMACH2TCR2_DSTAMODE_INCR (0x0000u)
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#define CSL_DMA_DMACH2TCR2_DSTAMODE_RSV1 (0x0001u)
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#define CSL_DMA_DMACH2TCR2_DSTAMODE_CONST (0x0002u)
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#define CSL_DMA_DMACH2TCR2_DSTAMODE_RSV3 (0x0003u)
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#define CSL_DMA_DMACH2TCR2_SRCAMODE_MASK (0x00C0u)
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#define CSL_DMA_DMACH2TCR2_SRCAMODE_SHIFT (0x0006u)
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#define CSL_DMA_DMACH2TCR2_SRCAMODE_RESETVAL (0x0000u)
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/*----SRCAMODE Tokens----*/
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#define CSL_DMA_DMACH2TCR2_SRCAMODE_INCR (0x0000u)
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#define CSL_DMA_DMACH2TCR2_SRCAMODE_RSV1 (0x0001u)
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#define CSL_DMA_DMACH2TCR2_SRCAMODE_CONST (0x0002u)
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#define CSL_DMA_DMACH2TCR2_SRCAMODE_RSV3 (0x0003u)
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#define CSL_DMA_DMACH2TCR2_BURSTMODE_MASK (0x0038u)
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#define CSL_DMA_DMACH2TCR2_BURSTMODE_SHIFT (0x0003u)
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#define CSL_DMA_DMACH2TCR2_BURSTMODE_RESETVAL (0x0000u)
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/*----BURSTMODE Tokens----*/
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#define CSL_DMA_DMACH2TCR2_BURSTMODE_1DWORD (0x0000u)
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#define CSL_DMA_DMACH2TCR2_BURSTMODE_2DWORDS (0x0001u)
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#define CSL_DMA_DMACH2TCR2_BURSTMODE_4DWORDS (0x0002u)
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#define CSL_DMA_DMACH2TCR2_BURSTMODE_8DWORDS (0x0003u)
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#define CSL_DMA_DMACH2TCR2_BURSTMODE_16DWORDS (0x0004u)
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#define CSL_DMA_DMACH2TCR2_BURSTMODE_RSV5 (0x0005u)
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#define CSL_DMA_DMACH2TCR2_BURSTMODE_RSV6 (0x0006u)
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#define CSL_DMA_DMACH2TCR2_BURSTMODE_RSV7 (0x0007u)
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#define CSL_DMA_DMACH2TCR2_SYNCMODE_MASK (0x0004u)
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#define CSL_DMA_DMACH2TCR2_SYNCMODE_SHIFT (0x0002u)
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#define CSL_DMA_DMACH2TCR2_SYNCMODE_RESETVAL (0x0000u)
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/*----SYNCMODE Tokens----*/
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#define CSL_DMA_DMACH2TCR2_SYNCMODE_NOSYNC (0x0000u)
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#define CSL_DMA_DMACH2TCR2_SYNCMODE_SYNC (0x0001u)
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#if (defined(CHIP_C5505_C5515) || defined(CHIP_C5504_C5514))
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#define CSL_DMA_DMACH2TCR2_LTSTATUS_MASK (0x0002u)
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#define CSL_DMA_DMACH2TCR2_LTSTATUS_SHIFT (0x0001u)
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#define CSL_DMA_DMACH2TCR2_LTSTATUS_RESETVAL (0x0000u)
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#define CSL_DMA_DMACH2TCR2_EPPMODE_MASK (0x0001u)
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#define CSL_DMA_DMACH2TCR2_EPPMODE_SHIFT (0x0000u)
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#define CSL_DMA_DMACH2TCR2_EPPMODE_RESETVAL (0x0000u)
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#endif
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#define CSL_DMA_DMACH2TCR2_RESETVAL (0x0000u)
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/* DMACH3SSAL */
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#define CSL_DMA_DMACH3SSAL_SSAL_MASK (0xFFFFu)
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#define CSL_DMA_DMACH3SSAL_SSAL_SHIFT (0x0000u)
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#define CSL_DMA_DMACH3SSAL_SSAL_RESETVAL (0x0000u)
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#define CSL_DMA_DMACH3SSAL_RESETVAL (0x0000u)
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/* DMACH3SSAU */
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#define CSL_DMA_DMACH3SSAU_SSAU_MASK (0xFFFFu)
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#define CSL_DMA_DMACH3SSAU_SSAU_SHIFT (0x0000u)
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#define CSL_DMA_DMACH3SSAU_SSAU_RESETVAL (0x0000u)
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#define CSL_DMA_DMACH3SSAU_RESETVAL (0x0000u)
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/* DMACH3DSAL */
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#define CSL_DMA_DMACH3DSAL_DSAL_MASK (0xFFFFu)
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#define CSL_DMA_DMACH3DSAL_DSAL_SHIFT (0x0000u)
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#define CSL_DMA_DMACH3DSAL_DSAL_RESETVAL (0x0000u)
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#define CSL_DMA_DMACH3DSAL_RESETVAL (0x0000u)
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/* DMACH3DSAU */
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#define CSL_DMA_DMACH3DSAU_DSAU_MASK (0xFFFFu)
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#define CSL_DMA_DMACH3DSAU_DSAU_SHIFT (0x0000u)
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#define CSL_DMA_DMACH3DSAU_DSAU_RESETVAL (0x0000u)
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#define CSL_DMA_DMACH3DSAU_RESETVAL (0x0000u)
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/* DMACH3TCR1 */
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#define CSL_DMA_DMACH3TCR1_LENGTH_MASK (0xFFFFu)
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#define CSL_DMA_DMACH3TCR1_LENGTH_SHIFT (0x0000u)
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#define CSL_DMA_DMACH3TCR1_LENGTH_RESETVAL (0x0000u)
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#define CSL_DMA_DMACH3TCR1_RESETVAL (0x0000u)
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/* DMACH3TCR2 */
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#define CSL_DMA_DMACH3TCR2_EN_MASK (0x8000u)
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#define CSL_DMA_DMACH3TCR2_EN_SHIFT (0x000Fu)
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#define CSL_DMA_DMACH3TCR2_EN_RESETVAL (0x0000u)
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/*----EN Tokens----*/
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#define CSL_DMA_DMACH3TCR2_EN_ENABLE (0x0000u)
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#define CSL_DMA_DMACH3TCR2_EN_DISABLE (0x0001u)
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#define CSL_DMA_DMACH3TCR2_STATUS_MASK (0x4000u)
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#define CSL_DMA_DMACH3TCR2_STATUS_SHIFT (0x000Eu)
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#define CSL_DMA_DMACH3TCR2_STATUS_RESETVAL (0x0000u)
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/*----STATUS Tokens----*/
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#define CSL_DMA_DMACH3TCR2_STATUS_DONE (0x0000u)
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#define CSL_DMA_DMACH3TCR2_STATUS_ACTIVE (0x0001u)
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#define CSL_DMA_DMACH3TCR2_INTEN_MASK (0x2000u)
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#define CSL_DMA_DMACH3TCR2_INTEN_SHIFT (0x000Du)
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#define CSL_DMA_DMACH3TCR2_INTEN_RESETVAL (0x0000u)
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/*----INTEN Tokens----*/
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#define CSL_DMA_DMACH3TCR2_INTEN_DISABLE (0x0000u)
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#define CSL_DMA_DMACH3TCR2_INTEN_ENABLE (0x0001u)
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#define CSL_DMA_DMACH3TCR2_AUTORLD_MASK (0x1000u)
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#define CSL_DMA_DMACH3TCR2_AUTORLD_SHIFT (0x000Cu)
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#define CSL_DMA_DMACH3TCR2_AUTORLD_RESETVAL (0x0000u)
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/*----AUTORLD Tokens----*/
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#define CSL_DMA_DMACH3TCR2_AUTORLD_DISABLE (0x0000u)
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#define CSL_DMA_DMACH3TCR2_AUTORLD_ENABLE (0x0001u)
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#define CSL_DMA_DMACH3TCR2_DSTAMODE_MASK (0x0300u)
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#define CSL_DMA_DMACH3TCR2_DSTAMODE_SHIFT (0x0008u)
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#define CSL_DMA_DMACH3TCR2_DSTAMODE_RESETVAL (0x0000u)
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/*----DSTAMODE Tokens----*/
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#define CSL_DMA_DMACH3TCR2_DSTAMODE_INCR (0x0000u)
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#define CSL_DMA_DMACH3TCR2_DSTAMODE_RSV1 (0x0001u)
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#define CSL_DMA_DMACH3TCR2_DSTAMODE_CONST (0x0002u)
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#define CSL_DMA_DMACH3TCR2_DSTAMODE_RSV3 (0x0003u)
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#define CSL_DMA_DMACH3TCR2_SRCAMODE_MASK (0x00C0u)
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#define CSL_DMA_DMACH3TCR2_SRCAMODE_SHIFT (0x0006u)
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#define CSL_DMA_DMACH3TCR2_SRCAMODE_RESETVAL (0x0000u)
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/*----SRCAMODE Tokens----*/
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#define CSL_DMA_DMACH3TCR2_SRCAMODE_INCR (0x0000u)
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#define CSL_DMA_DMACH3TCR2_SRCAMODE_RSV1 (0x0001u)
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#define CSL_DMA_DMACH3TCR2_SRCAMODE_CONST (0x0002u)
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#define CSL_DMA_DMACH3TCR2_SRCAMODE_RSV3 (0x0003u)
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#define CSL_DMA_DMACH3TCR2_BURSTMODE_MASK (0x0038u)
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#define CSL_DMA_DMACH3TCR2_BURSTMODE_SHIFT (0x0003u)
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#define CSL_DMA_DMACH3TCR2_BURSTMODE_RESETVAL (0x0000u)
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/*----BURSTMODE Tokens----*/
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#define CSL_DMA_DMACH3TCR2_BURSTMODE_1DWORD (0x0000u)
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#define CSL_DMA_DMACH3TCR2_BURSTMODE_2DWORDS (0x0001u)
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#define CSL_DMA_DMACH3TCR2_BURSTMODE_4DWORDS (0x0002u)
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#define CSL_DMA_DMACH3TCR2_BURSTMODE_8DWORDS (0x0003u)
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#define CSL_DMA_DMACH3TCR2_BURSTMODE_16DWORDS (0x0004u)
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#define CSL_DMA_DMACH3TCR2_BURSTMODE_RSV5 (0x0005u)
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#define CSL_DMA_DMACH3TCR2_BURSTMODE_RSV6 (0x0006u)
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#define CSL_DMA_DMACH3TCR2_BURSTMODE_RSV7 (0x0007u)
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#define CSL_DMA_DMACH3TCR2_SYNCMODE_MASK (0x0004u)
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#define CSL_DMA_DMACH3TCR2_SYNCMODE_SHIFT (0x0002u)
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#define CSL_DMA_DMACH3TCR2_SYNCMODE_RESETVAL (0x0000u)
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/*----SYNCMODE Tokens----*/
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#define CSL_DMA_DMACH3TCR2_SYNCMODE_NOSYNC (0x0000u)
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#define CSL_DMA_DMACH3TCR2_SYNCMODE_SYNC (0x0001u)
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#if (defined(CHIP_C5505_C5515) || defined(CHIP_C5504_C5514))
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#define CSL_DMA_DMACH3TCR2_LTSTATUS_MASK (0x0002u)
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#define CSL_DMA_DMACH3TCR2_LTSTATUS_SHIFT (0x0001u)
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#define CSL_DMA_DMACH3TCR2_LTSTATUS_RESETVAL (0x0000u)
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#define CSL_DMA_DMACH3TCR2_EPPMODE_MASK (0x0001u)
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#define CSL_DMA_DMACH3TCR2_EPPMODE_SHIFT (0x0000u)
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#define CSL_DMA_DMACH3TCR2_EPPMODE_RESETVAL (0x0000u)
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#endif
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#define CSL_DMA_DMACH3TCR2_RESETVAL (0x0000u)
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#endif
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