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https://github.com/QuantumLeaps/qpcpp.git
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345 lines
11 KiB
C
345 lines
11 KiB
C
/********************************************************************
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* Copyright (C) 2003-2008 Texas Instruments Incorporated.
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* All Rights Reserved
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*********************************************************************
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* file: cslr_uart.h
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*
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* Brief: This file contains the Register Description for uart
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*
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*********************************************************************/
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#ifndef _CSLR_UART_H_
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#define _CSLR_UART_H_
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#include <cslr.h>
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#include <tistdtypes.h>
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#include <csl_general.h>
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/* Minimum unit = 2 bytes */
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/**************************************************************************\
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* Register Overlay Structure
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\**************************************************************************/
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typedef struct {
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volatile Uint16 THR;
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volatile Uint16 RSVD0;
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volatile Uint16 IER;
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volatile Uint16 RSVD1;
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volatile Uint16 FCR;
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volatile Uint16 RSVD2;
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volatile Uint16 LCR;
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volatile Uint16 RSVD3;
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volatile Uint16 MCR;
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volatile Uint16 RSVD4;
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volatile Uint16 LSR;
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volatile Uint16 RSVD5[3];
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volatile Uint16 SCR;
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volatile Uint16 RSVD6;
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volatile Uint16 DLL;
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volatile Uint16 RSVD7;
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volatile Uint16 DLH;
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volatile Uint16 RSVD8[5];
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volatile Uint16 PWREMU_MGMT;
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} CSL_UartRegs;
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/**************************************************************************\
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* Field Definition Macros
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\**************************************************************************/
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/* THR */
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#define CSL_UART_THR_DATA_MASK (0x00FFu)
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#define CSL_UART_THR_DATA_SHIFT (0x0000u)
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#define CSL_UART_THR_DATA_RESETVAL (0x0000u)
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#define CSL_UART_THR_RESETVAL (0x0000u)
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/* RBR */
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#define CSL_UART_RBR_DATA_MASK (0x00FFu)
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#define CSL_UART_RBR_DATA_SHIFT (0x0000u)
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#define CSL_UART_RBR_DATA_RESETVAL (0x0000u)
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#define CSL_UART_RBR_RESETVAL (0x0000u)
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/* IER */
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#define CSL_UART_IER_ELSI_MASK (0x0004u)
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#define CSL_UART_IER_ELSI_SHIFT (0x0002u)
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#define CSL_UART_IER_ELSI_RESETVAL (0x0000u)
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/*----ELSI Tokens----*/
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#define CSL_UART_IER_ELSI_DISABLE (0x0000u)
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#define CSL_UART_IER_ELSI_ENABLE (0x0001u)
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#define CSL_UART_IER_ETBEI_MASK (0x0002u)
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#define CSL_UART_IER_ETBEI_SHIFT (0x0001u)
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#define CSL_UART_IER_ETBEI_RESETVAL (0x0000u)
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/*----ETBEI Tokens----*/
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#define CSL_UART_IER_ETBEI_DISABLE (0x0000u)
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#define CSL_UART_IER_ETBEI_ENABLE (0x0001u)
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#define CSL_UART_IER_ERBI_MASK (0x0001u)
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#define CSL_UART_IER_ERBI_SHIFT (0x0000u)
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#define CSL_UART_IER_ERBI_RESETVAL (0x0000u)
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/*----ERBI Tokens----*/
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#define CSL_UART_IER_ERBI_DISABLE (0x0000u)
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#define CSL_UART_IER_ERBI_ENABLE (0x0001u)
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#define CSL_UART_IER_RESETVAL (0x0000u)
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/* FCR */
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#define CSL_UART_FCR_RXFIFTL_MASK (0x00C0u)
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#define CSL_UART_FCR_RXFIFTL_SHIFT (0x0006u)
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#define CSL_UART_FCR_RXFIFTL_RESETVAL (0x0000u)
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/*----RXFIFTL Tokens----*/
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#define CSL_UART_FCR_RXFIFTL_CHAR1 (0x0000u)
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#define CSL_UART_FCR_RXFIFTL_CHAR4 (0x0001u)
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#define CSL_UART_FCR_RXFIFTL_CHAR8 (0x0002u)
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#define CSL_UART_FCR_RXFIFTL_CHAR14 (0x0003u)
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#define CSL_UART_FCR_DMAMODE1_MASK (0x0008u)
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#define CSL_UART_FCR_DMAMODE1_SHIFT (0x0003u)
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#define CSL_UART_FCR_DMAMODE1_RESETVAL (0x0000u)
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/*----DMAMODE1 Tokens----*/
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#define CSL_UART_FCR_DMAMODE1_DISABLE (0x0000u)
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#define CSL_UART_FCR_DMAMODE1_ENABLE (0x0001u)
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#define CSL_UART_FCR_TXCLR_MASK (0x0004u)
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#define CSL_UART_FCR_TXCLR_SHIFT (0x0002u)
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#define CSL_UART_FCR_TXCLR_RESETVAL (0x0000u)
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/*----TXCLR Tokens----*/
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#define CSL_UART_FCR_TXCLR_CLR (0x0001u)
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#define CSL_UART_FCR_RXCLR_MASK (0x0002u)
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#define CSL_UART_FCR_RXCLR_SHIFT (0x0001u)
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#define CSL_UART_FCR_RXCLR_RESETVAL (0x0000u)
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/*----RXCLR Tokens----*/
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#define CSL_UART_FCR_RXCLR_CLR (0x0001u)
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#define CSL_UART_FCR_FIFOEN_MASK (0x0001u)
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#define CSL_UART_FCR_FIFOEN_SHIFT (0x0000u)
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#define CSL_UART_FCR_FIFOEN_RESETVAL (0x0000u)
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/*----FIFOEN Tokens----*/
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#define CSL_UART_FCR_FIFOEN_DISABLE (0x0000u)
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#define CSL_UART_FCR_FIFOEN_ENABLE (0x0001u)
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#define CSL_UART_FCR_RESETVAL (0x0000u)
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/* IIR */
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#define CSL_UART_IIR_FIFOEN_MASK (0x00C0u)
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#define CSL_UART_IIR_FIFOEN_SHIFT (0x0006u)
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#define CSL_UART_IIR_FIFOEN_RESETVAL (0x0000u)
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/*----FIFOEN Tokens----*/
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#define CSL_UART_IIR_FIFOEN_DISABLED (0x0000u)
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#define CSL_UART_IIR_FIFOEN_ENABLED (0x0001u)
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#define CSL_UART_IIR_INTID_MASK (0x000Eu)
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#define CSL_UART_IIR_INTID_SHIFT (0x0001u)
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#define CSL_UART_IIR_INTID_RESETVAL (0x0000u)
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/*----INTID Tokens----*/
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#define CSL_UART_IIR_INTID_RSV0 (0x0000u)
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#define CSL_UART_IIR_INTID_THRE (0x0001u)
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#define CSL_UART_IIR_INTID_RDA (0x0002u)
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#define CSL_UART_IIR_INTID_RLS (0x0003u)
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#define CSL_UART_IIR_INTID_RSV4 (0x0004u)
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#define CSL_UART_IIR_INTID_RSV5 (0x0005u)
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#define CSL_UART_IIR_INTID_CTI (0x0006u)
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#define CSL_UART_IIR_INTID_RSV7 (0x0007u)
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#define CSL_UART_IIR_IPEND_MASK (0x0001u)
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#define CSL_UART_IIR_IPEND_SHIFT (0x0000u)
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#define CSL_UART_IIR_IPEND_RESETVAL (0x0001u)
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/*----IPEND Tokens----*/
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#define CSL_UART_IIR_IPEND_PENDING (0x0000u)
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#define CSL_UART_IIR_IPEND_NONE (0x0001u)
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#define CSL_UART_IIR_RESETVAL (0x0001u)
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/* LCR */
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#define CSL_UART_LCR_DLAB_MASK (0x0080u)
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#define CSL_UART_LCR_DLAB_SHIFT (0x0007u)
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#define CSL_UART_LCR_DLAB_RESETVAL (0x0000u)
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/*----DLAB Tokens----*/
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#define CSL_UART_LCR_DLAB_DLABON (0x0000u)
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#define CSL_UART_LCR_DLAB_DLABOFF (0x0001u)
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#define CSL_UART_LCR_BC_MASK (0x0040u)
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#define CSL_UART_LCR_BC_SHIFT (0x0006u)
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#define CSL_UART_LCR_BC_RESETVAL (0x0000u)
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/*----BC Tokens----*/
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#define CSL_UART_LCR_BC_DISABLE (0x0000u)
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#define CSL_UART_LCR_BC_ENABLE (0x0001u)
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#define CSL_UART_LCR_SP_MASK (0x0020u)
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#define CSL_UART_LCR_SP_SHIFT (0x0005u)
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#define CSL_UART_LCR_SP_RESETVAL (0x0000u)
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/*----SP Tokens----*/
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#define CSL_UART_LCR_SP_DISABLE (0x0000u)
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#define CSL_UART_LCR_SP_ENABLE (0x0001u)
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#define CSL_UART_LCR_EPS_MASK (0x0010u)
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#define CSL_UART_LCR_EPS_SHIFT (0x0004u)
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#define CSL_UART_LCR_EPS_RESETVAL (0x0000u)
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/*----EPS Tokens----*/
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#define CSL_UART_LCR_EPS_ODD (0x0000u)
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#define CSL_UART_LCR_EPS_EVEN (0x0001u)
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#define CSL_UART_LCR_PEN_MASK (0x0008u)
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#define CSL_UART_LCR_PEN_SHIFT (0x0003u)
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#define CSL_UART_LCR_PEN_RESETVAL (0x0000u)
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/*----PEN Tokens----*/
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#define CSL_UART_LCR_PEN_DISABLE (0x0000u)
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#define CSL_UART_LCR_PEN_ENABLE (0x0001u)
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#define CSL_UART_LCR_STB_MASK (0x0004u)
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#define CSL_UART_LCR_STB_SHIFT (0x0002u)
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#define CSL_UART_LCR_STB_RESETVAL (0x0000u)
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/*----STB Tokens----*/
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#define CSL_UART_LCR_STB_1STOPBIT (0x0000u)
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#define CSL_UART_LCR_STB_MULTSTOPBIT (0x0001u)
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#define CSL_UART_LCR_WLS_MASK (0x0003u)
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#define CSL_UART_LCR_WLS_SHIFT (0x0000u)
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#define CSL_UART_LCR_WLS_RESETVAL (0x0000u)
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/*----WLS Tokens----*/
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#define CSL_UART_LCR_WLS_BITS5 (0x0000u)
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#define CSL_UART_LCR_WLS_BITS6 (0x0001u)
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#define CSL_UART_LCR_WLS_BITS7 (0x0002u)
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#define CSL_UART_LCR_WLS_BITS8 (0x0003u)
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#define CSL_UART_LCR_RESETVAL (0x0000u)
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/* MCR */
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#define CSL_UART_MCR_AFE_MASK (0x0020u)
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#define CSL_UART_MCR_AFE_SHIFT (0x0005u)
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#define CSL_UART_MCR_AFE_RESETVAL (0x0000u)
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/*----AFE Tokens----*/
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#define CSL_UART_MCR_AFE_DISABLE (0x0000u)
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#define CSL_UART_MCR_AFE_ENABLE (0x0001u)
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#define CSL_UART_MCR_LOOP_MASK (0x0010u)
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#define CSL_UART_MCR_LOOP_SHIFT (0x0004u)
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#define CSL_UART_MCR_LOOP_RESETVAL (0x0000u)
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/*----LOOP Tokens----*/
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#define CSL_UART_MCR_LOOP_DISABLE (0x0000u)
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#define CSL_UART_MCR_LOOP_ENABLE (0x0001u)
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#define CSL_UART_MCR_RTS_MASK (0x0002u)
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#define CSL_UART_MCR_RTS_SHIFT (0x0001u)
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#define CSL_UART_MCR_RTS_RESETVAL (0x0000u)
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/*----RTS Tokens----*/
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#define CSL_UART_MCR_RTS_CTSEN (0x0000u)
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#define CSL_UART_MCR_RTS_CTSRTSEN (0x0001u)
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#define CSL_UART_MCR_RESETVAL (0x0000u)
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/* LSR */
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#define CSL_UART_LSR_RXFIFOE_MASK (0x0080u)
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#define CSL_UART_LSR_RXFIFOE_SHIFT (0x0007u)
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#define CSL_UART_LSR_RXFIFOE_RESETVAL (0x0000u)
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#define CSL_UART_LSR_TEMT_MASK (0x0040u)
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#define CSL_UART_LSR_TEMT_SHIFT (0x0006u)
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#define CSL_UART_LSR_TEMT_RESETVAL (0x0001u)
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#define CSL_UART_LSR_THRE_MASK (0x0020u)
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#define CSL_UART_LSR_THRE_SHIFT (0x0005u)
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#define CSL_UART_LSR_THRE_RESETVAL (0x0001u)
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#define CSL_UART_LSR_BI_MASK (0x0010u)
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#define CSL_UART_LSR_BI_SHIFT (0x0004u)
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#define CSL_UART_LSR_BI_RESETVAL (0x0000u)
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#define CSL_UART_LSR_FE_MASK (0x0008u)
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#define CSL_UART_LSR_FE_SHIFT (0x0003u)
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#define CSL_UART_LSR_FE_RESETVAL (0x0000u)
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#define CSL_UART_LSR_PE_MASK (0x0004u)
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#define CSL_UART_LSR_PE_SHIFT (0x0002u)
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#define CSL_UART_LSR_PE_RESETVAL (0x0000u)
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#define CSL_UART_LSR_OE_MASK (0x0002u)
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#define CSL_UART_LSR_OE_SHIFT (0x0001u)
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#define CSL_UART_LSR_OE_RESETVAL (0x0000u)
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#define CSL_UART_LSR_DR_MASK (0x0001u)
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#define CSL_UART_LSR_DR_SHIFT (0x0000u)
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#define CSL_UART_LSR_DR_RESETVAL (0x0000u)
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#define CSL_UART_LSR_RESETVAL (0x0060u)
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/* SCR */
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#define CSL_UART_SCR_DATA_MASK (0x00FFu)
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#define CSL_UART_SCR_DATA_SHIFT (0x0000u)
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#define CSL_UART_SCR_DATA_RESETVAL (0x0000u)
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#define CSL_UART_SCR_RESETVAL (0x0000u)
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/* DLL */
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#define CSL_UART_DLL_DLL_MASK (0x00FFu)
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#define CSL_UART_DLL_DLL_SHIFT (0x0000u)
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#define CSL_UART_DLL_DLL_RESETVAL (0x0000u)
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#define CSL_UART_DLL_RESETVAL (0x0000u)
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/* DLH */
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#define CSL_UART_DLH_DLH_MASK (0x00FFu)
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#define CSL_UART_DLH_DLH_SHIFT (0x0000u)
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#define CSL_UART_DLH_DLH_RESETVAL (0x0000u)
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#define CSL_UART_DLH_RESETVAL (0x0000u)
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/* PWREMU_MGMT */
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#define CSL_UART_PWREMU_MGMT_UTRST_MASK (0x4000u)
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#define CSL_UART_PWREMU_MGMT_UTRST_SHIFT (0x000Eu)
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#define CSL_UART_PWREMU_MGMT_UTRST_RESETVAL (0x0000u)
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/*----UTRST Tokens----*/
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#define CSL_UART_PWREMU_MGMT_UTRST_RESET (0x0000u)
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#define CSL_UART_PWREMU_MGMT_UTRST_ENABLE (0x0001u)
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#define CSL_UART_PWREMU_MGMT_URRST_MASK (0x2000u)
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#define CSL_UART_PWREMU_MGMT_URRST_SHIFT (0x000Du)
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#define CSL_UART_PWREMU_MGMT_URRST_RESETVAL (0x0000u)
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/*----URRST Tokens----*/
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#define CSL_UART_PWREMU_MGMT_URRST_RESET (0x0000u)
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#define CSL_UART_PWREMU_MGMT_URRST_ENABLE (0x0001u)
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#define CSL_UART_PWREMU_MGMT_FREE_MASK (0x0001u)
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#define CSL_UART_PWREMU_MGMT_FREE_SHIFT (0x0000u)
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#define CSL_UART_PWREMU_MGMT_FREE_RESETVAL (0x0000u)
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/*----FREE Tokens----*/
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#define CSL_UART_PWREMU_MGMT_FREE_STOP (0x0000u)
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#define CSL_UART_PWREMU_MGMT_FREE_RUN (0x0001u)
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#define CSL_UART_PWREMU_MGMT_RESETVAL (0x0000u)
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#endif
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