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249 lines
8.3 KiB
Plaintext
249 lines
8.3 KiB
Plaintext
Express Logic's ThreadX for ST's STM32F4 Discovery Evaluation Board (Cortex-M4)
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Using the IAR Tools
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*** DEMO VERSION ***
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0. About This Version
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This version of ThreadX is for demonstration purposes only and may not
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be used for any product development, either directly or indirectly. In
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addition, this demonstration may not be used for any competitive purpose.
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1. Installation
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ThreadX for ST's STM32F4 Discovery (Cortex-M4) is pre-installed in the evaluation
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package.
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2. Building the ThreadX run-time Library
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This demonstration version contains a pre-built ThreadX library, tx.a. The library is
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intended for demonstration purposes only and thus has the following limitations:
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10 Threads
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10 Timers
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10 Event Flag Groups
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10 Mutexes
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10 Queues
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10 Semaphores
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10 Block Pool
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10 Byte Pool
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3. Demonstration System
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The ThreadX demonstration is designed to execute on the STM32F4 Discovery evaluation
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board under the IAR Windows-based debugger.
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Building the demonstration is easy; simply make the demo_threadx.ewp project
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the "active project" in the IAR Embedded Workbench and select the "Make" button.
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You should observe the compilation of demo_threadx.c (which is the demonstration
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application) and linking with tx.a. The resulting file demo_threadx.out is a binary
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file that can be downloaded and executed on the STM32F4 Discovery evaluation board using
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the IAR debugger.
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4. System Initialization
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The entry point in ThreadX for the (Cortex-M4) using IAR tools is at label
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Reset_Handler. This is defined within the STM32 startup code, namely
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the file startup_stm32f429xx.s. From this entry point, the IAR startup code
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at __iar_program_start is called. This is where all static and global preset
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C variable initialization processing takes place.
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The ThreadX tx_initialize_low_level.s file is responsible for setting up
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various system data structures, and a periodic timer interrupt source.
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The _tx_initialize_low_level function inside of tx_initialize_low_level.s
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also determines the first available address for use by the application, which
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is supplied as the sole input parameter to your application definition function,
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tx_application_define. To accomplish this, a section is created in
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tx_initialize_low_level.s called FREE_MEM, which must be located after all
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other RAM sections in memory.
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5. Register Usage and Stack Frames
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The following defines the saved context stack frames for context switches
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that occur as a result of interrupt handling or from thread-level API calls.
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All suspended threads have the same stack frame in the Cortex-M4 version of
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ThreadX. The top of the suspended thread's stack is pointed to by
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tx_thread_stack_ptr in the associated thread control block TX_THREAD.
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Non-FPU Stack Frame:
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Stack Offset Stack Contents
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0x00 LR Interrupted LR (LR at time of PENDSV)
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0x04 r4
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0x08 r5
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0x0C r6
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0x10 r7
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0x14 r8
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0x18 r9
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0x1C r10 (sl)
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0x20 r11
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0x24 r0 (Hardware stack starts here!!)
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0x28 r1
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0x2C r2
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0x30 r3
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0x34 r12
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0x38 lr
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0x3C pc
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0x40 xPSR
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FPU Stack Frame (only interrupted thread with FPU enabled):
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Stack Offset Stack Contents
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0x00 LR Interrupted LR (LR at time of PENDSV)
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0x04 s0
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0x08 s1
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0x0C s2
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0x10 s3
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0x14 s4
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0x18 s5
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0x1C s6
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0x20 s7
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0x24 s8
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0x28 s9
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0x2C s10
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0x30 s11
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0x34 s12
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0x38 s13
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0x3C s14
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0x40 s15
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0x44 s16
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0x48 s17
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0x4C s18
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0x50 s19
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0x54 s20
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0x58 s21
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0x5C s22
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0x60 s23
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0x64 s24
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0x68 s25
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0x6C s26
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0x70 s27
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0x74 s28
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0x78 s29
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0x7C s30
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0x80 s31
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0x84 fpscr
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0x88 r4
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0x8C r5
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0x90 r6
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0x94 r7
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0x98 r8
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0x9C r9
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0xA0 r10 (sl)
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0xA4 r11
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0xA8 r0 (Hardware stack starts here!!)
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0xAC r1
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0xB0 r2
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0xB4 r3
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0xB8 r12
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0xBC lr
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0xC0 pc
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0xC4 xPSR
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6. Improving Performance
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The distribution version of ThreadX is built without any compiler
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optimizations. This makes it easy to debug because you can trace or set
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breakpoints inside of ThreadX itself. Of course, this costs some
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performance. To make it run faster, you can change the ThreadX library
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project to enable various compiler optimizations.
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In addition, you can eliminate the ThreadX basic API error checking by
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compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING
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defined.
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7. Interrupt Handling
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The Cortex-M4 vectors start at the label __vector_table and is defined in cstartup_M.s.
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The application may modify the vector area according to its needs.
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7.2 Managed Interrupts
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From version 5.6 going forward, ISRs for Cortex-M using the IAR tools can be written
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completely in C (or assembly language) without any calls to _tx_thread_context_save or
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_tx_thread_context_restore. These ISRs are allowed access to the ThreadX API that is
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available to ISRs.
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ISRs written in C will take the form (where "your_C_isr" is an entry in the vector table):
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void your_C_isr(void)
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{
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/* ISR processing goes here, including any needed function calls. */
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}
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ISRs written in assembly language will take the form:
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PUBLIC your_assembly_isr
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your_assembly_isr:
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PUSH {lr}
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; ISR processing goes here, including any needed function calls.
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POP {lr}
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BX lr
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Backward compatibility to the previous style assembly ISRs is maintained, which was of
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the form:
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PUBLIC __legacy_isr_handler
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__legacy_isr_handler:
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PUSH {lr}
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BL _tx_thread_context_save
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; /* Do interrupt handler work here */
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; /* .... */
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B _tx_thread_context_restore
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8. IAR Thread-safe Library Support
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Thread-safe support for the IAR tools is easily enabled by building the ThreadX library
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and the application with TX_ENABLE_IAR_LIBRARY_SUPPORT. Also, the linker control file
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should have the following line added (if not already in place):
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initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application
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The project options "General Options -> Library Configuration" should also have the
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"Enable thread support in library" box selected.
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9. VFP Support
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When applicable, ThreadX for the STM32F4 Discovery (Cortex-M4) supports lazy VFP support, which
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means that applications threads can simply use the VFP and ThreadX automatically maintains
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the VFP registers as part of the thread context - no additional setup by the application
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is required.
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10. Revision History
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08/01/2017 Initial ThreadX version for STM32F4 Discovery (Cortex-M4) using IAR's ARM tools.
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Copyright(c) 1996-2017 Express Logic, Inc.
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Express Logic, Inc.
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11323 West Bernardo Court
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San Diego, CA 92127
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www.expresslogic.com
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