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803 lines
24 KiB
C
803 lines
24 KiB
C
/** @file esm.c
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* @brief Esm Driver Source File
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* @date 02-Mar-2016
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* @version 04.05.02
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*
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* This file contains:
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* - API Functions
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* .
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* which are relevant for the Esm driver.
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*/
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/*
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* Copyright (C) 2009-2016 Texas Instruments Incorporated - www.ti.com
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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*
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* Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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/* USER CODE BEGIN (0) */
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/* USER CODE END */
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/* Include Files */
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#include "esm.h"
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#include "sys_vim.h"
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/* USER CODE BEGIN (1) */
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/* USER CODE END */
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/** @fn void esmInit(void)
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* @brief Initializes Esm Driver
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*
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* This function initializes the Esm driver.
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*
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*/
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/* USER CODE BEGIN (2) */
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/* USER CODE END */
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/* SourceId : ESM_SourceId_001 */
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/* DesignId : ESM_DesignId_001 */
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/* Requirements : HL_SR4 */
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void esmInit(void)
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{
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/* USER CODE BEGIN (3) */
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/* USER CODE END */
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/** - Disable error pin channels */
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esmREG->DEPAPR1 = 0xFFFFFFFFU;
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esmREG->IEPCR4 = 0xFFFFFFFFU;
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/** - Disable interrupts */
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esmREG->IECR1 = 0xFFFFFFFFU;
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esmREG->IECR4 = 0xFFFFFFFFU;
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/** - Clear error status flags */
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esmREG->SR1[0U] = 0xFFFFFFFFU;
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esmREG->SR1[1U] = 0xFFFFFFFFU;
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esmREG->SSR2 = 0xFFFFFFFFU;
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esmREG->SR1[2U] = 0xFFFFFFFFU;
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esmREG->SR4[0U] = 0xFFFFFFFFU;
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/** - Setup LPC preload */
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esmREG->LTCPR = 16384U - 1U;
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/** - Reset error pin */
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if (esmREG->EPSR == 0U)
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{
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esmREG->EKR = 0x00000005U;
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}
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else
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{
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esmREG->EKR = 0x00000000U;
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}
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/** - Clear interrupt level */
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esmREG->ILCR1 = 0xFFFFFFFFU;
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esmREG->ILCR4 = 0xFFFFFFFFU;
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/** - Set interrupt level */
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esmREG->ILSR1 = (uint32)((uint32)0U << 31U)
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| (uint32)((uint32)0U << 30U)
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| (uint32)((uint32)0U << 29U)
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| (uint32)((uint32)0U << 28U)
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| (uint32)((uint32)0U << 27U)
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| (uint32)((uint32)0U << 26U)
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| (uint32)((uint32)0U << 25U)
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| (uint32)((uint32)0U << 24U)
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| (uint32)((uint32)0U << 23U)
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| (uint32)((uint32)0U << 22U)
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| (uint32)((uint32)0U << 21U)
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| (uint32)((uint32)0U << 20U)
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| (uint32)((uint32)0U << 19U)
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| (uint32)((uint32)0U << 18U)
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| (uint32)((uint32)0U << 17U)
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| (uint32)((uint32)0U << 16U)
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| (uint32)((uint32)0U << 15U)
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| (uint32)((uint32)0U << 14U)
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| (uint32)((uint32)0U << 13U)
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| (uint32)((uint32)0U << 12U)
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| (uint32)((uint32)0U << 11U)
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| (uint32)((uint32)0U << 10U)
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| (uint32)((uint32)0U << 9U)
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| (uint32)((uint32)0U << 8U)
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| (uint32)((uint32)0U << 7U)
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| (uint32)((uint32)0U << 6U)
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| (uint32)((uint32)0U << 5U)
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| (uint32)((uint32)0U << 4U)
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| (uint32)((uint32)0U << 3U)
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| (uint32)((uint32)0U << 2U)
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| (uint32)((uint32)0U << 1U)
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| (uint32)((uint32)0U << 0U);
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esmREG->ILSR4 = (uint32)((uint32)0U << 31U)
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| (uint32)((uint32)0U << 30U)
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| (uint32)((uint32)0U << 29U)
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| (uint32)((uint32)0U << 28U)
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| (uint32)((uint32)0U << 27U)
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| (uint32)((uint32)0U << 26U)
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| (uint32)((uint32)0U << 25U)
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| (uint32)((uint32)0U << 24U)
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| (uint32)((uint32)0U << 23U)
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| (uint32)((uint32)0U << 22U)
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| (uint32)((uint32)0U << 21U)
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| (uint32)((uint32)0U << 20U)
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| (uint32)((uint32)0U << 19U)
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| (uint32)((uint32)0U << 18U)
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| (uint32)((uint32)0U << 17U)
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| (uint32)((uint32)0U << 16U)
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| (uint32)((uint32)0U << 15U)
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| (uint32)((uint32)0U << 14U)
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| (uint32)((uint32)0U << 13U)
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| (uint32)((uint32)0U << 12U)
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| (uint32)((uint32)0U << 11U)
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| (uint32)((uint32)0U << 10U)
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| (uint32)((uint32)0U << 9U)
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| (uint32)((uint32)0U << 8U)
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| (uint32)((uint32)0U << 7U)
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| (uint32)((uint32)0U << 6U)
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| (uint32)((uint32)0U << 5U)
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| (uint32)((uint32)0U << 4U)
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| (uint32)((uint32)0U << 3U)
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| (uint32)((uint32)0U << 2U)
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| (uint32)((uint32)0U << 1U)
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| (uint32)((uint32)0U << 0U);
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/** - Enable error pin channels */
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esmREG->EEPAPR1 = (uint32)((uint32)0U << 31U)
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| (uint32)((uint32)0U << 30U)
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| (uint32)((uint32)0U << 29U)
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| (uint32)((uint32)0U << 28U)
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| (uint32)((uint32)0U << 27U)
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| (uint32)((uint32)0U << 26U)
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| (uint32)((uint32)0U << 25U)
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| (uint32)((uint32)0U << 24U)
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| (uint32)((uint32)0U << 23U)
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| (uint32)((uint32)0U << 22U)
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| (uint32)((uint32)0U << 21U)
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| (uint32)((uint32)0U << 20U)
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| (uint32)((uint32)0U << 19U)
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| (uint32)((uint32)0U << 18U)
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| (uint32)((uint32)0U << 17U)
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| (uint32)((uint32)0U << 16U)
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| (uint32)((uint32)0U << 15U)
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| (uint32)((uint32)0U << 14U)
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| (uint32)((uint32)0U << 13U)
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| (uint32)((uint32)0U << 12U)
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| (uint32)((uint32)0U << 11U)
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| (uint32)((uint32)0U << 10U)
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| (uint32)((uint32)0U << 9U)
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| (uint32)((uint32)0U << 8U)
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| (uint32)((uint32)0U << 7U)
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| (uint32)((uint32)0U << 6U)
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| (uint32)((uint32)0U << 5U)
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| (uint32)((uint32)0U << 4U)
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| (uint32)((uint32)0U << 3U)
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| (uint32)((uint32)0U << 2U)
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| (uint32)((uint32)0U << 1U)
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| (uint32)((uint32)0U << 0U);
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esmREG->IEPSR4 = (uint32)((uint32)0U << 31U)
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| (uint32)((uint32)0U << 30U)
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| (uint32)((uint32)0U << 29U)
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| (uint32)((uint32)0U << 28U)
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| (uint32)((uint32)0U << 27U)
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| (uint32)((uint32)0U << 26U)
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| (uint32)((uint32)0U << 25U)
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| (uint32)((uint32)0U << 24U)
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| (uint32)((uint32)0U << 23U)
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| (uint32)((uint32)0U << 22U)
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| (uint32)((uint32)0U << 21U)
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| (uint32)((uint32)0U << 20U)
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| (uint32)((uint32)0U << 19U)
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| (uint32)((uint32)0U << 18U)
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| (uint32)((uint32)0U << 17U)
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| (uint32)((uint32)0U << 16U)
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| (uint32)((uint32)0U << 15U)
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| (uint32)((uint32)0U << 14U)
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| (uint32)((uint32)0U << 13U)
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| (uint32)((uint32)0U << 12U)
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| (uint32)((uint32)0U << 11U)
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| (uint32)((uint32)0U << 10U)
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| (uint32)((uint32)0U << 9U)
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| (uint32)((uint32)0U << 8U)
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| (uint32)((uint32)0U << 7U)
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| (uint32)((uint32)0U << 6U)
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| (uint32)((uint32)0U << 5U)
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| (uint32)((uint32)0U << 4U)
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| (uint32)((uint32)0U << 3U)
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| (uint32)((uint32)0U << 2U)
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| (uint32)((uint32)0U << 1U)
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| (uint32)((uint32)0U << 0U);
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/** - Enable interrupts */
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esmREG->IESR1 = (uint32)((uint32)0U << 31U)
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| (uint32)((uint32)0U << 30U)
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| (uint32)((uint32)0U << 29U)
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| (uint32)((uint32)0U << 28U)
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| (uint32)((uint32)0U << 27U)
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| (uint32)((uint32)0U << 26U)
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| (uint32)((uint32)0U << 25U)
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| (uint32)((uint32)0U << 24U)
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| (uint32)((uint32)0U << 23U)
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| (uint32)((uint32)0U << 22U)
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| (uint32)((uint32)0U << 21U)
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| (uint32)((uint32)0U << 20U)
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| (uint32)((uint32)0U << 19U)
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| (uint32)((uint32)0U << 18U)
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| (uint32)((uint32)0U << 17U)
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| (uint32)((uint32)0U << 16U)
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| (uint32)((uint32)0U << 15U)
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| (uint32)((uint32)0U << 14U)
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| (uint32)((uint32)0U << 13U)
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| (uint32)((uint32)0U << 12U)
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| (uint32)((uint32)0U << 11U)
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| (uint32)((uint32)0U << 10U)
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| (uint32)((uint32)0U << 9U)
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| (uint32)((uint32)0U << 8U)
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| (uint32)((uint32)0U << 7U)
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| (uint32)((uint32)0U << 6U)
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| (uint32)((uint32)0U << 5U)
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| (uint32)((uint32)0U << 4U)
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| (uint32)((uint32)0U << 3U)
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| (uint32)((uint32)0U << 2U)
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| (uint32)((uint32)0U << 1U)
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| (uint32)((uint32)0U << 0U);
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esmREG->IESR4 = (uint32)((uint32)0U << 31U)
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| (uint32)((uint32)0U << 30U)
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| (uint32)((uint32)0U << 29U)
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| (uint32)((uint32)0U << 28U)
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| (uint32)((uint32)0U << 27U)
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| (uint32)((uint32)0U << 26U)
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| (uint32)((uint32)0U << 25U)
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| (uint32)((uint32)0U << 24U)
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| (uint32)((uint32)0U << 23U)
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| (uint32)((uint32)0U << 22U)
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| (uint32)((uint32)0U << 21U)
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| (uint32)((uint32)0U << 20U)
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| (uint32)((uint32)0U << 19U)
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| (uint32)((uint32)0U << 18U)
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| (uint32)((uint32)0U << 17U)
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| (uint32)((uint32)0U << 16U)
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| (uint32)((uint32)0U << 15U)
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| (uint32)((uint32)0U << 14U)
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| (uint32)((uint32)0U << 13U)
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| (uint32)((uint32)0U << 12U)
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| (uint32)((uint32)0U << 11U)
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| (uint32)((uint32)0U << 10U)
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| (uint32)((uint32)0U << 9U)
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| (uint32)((uint32)0U << 8U)
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| (uint32)((uint32)0U << 7U)
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| (uint32)((uint32)0U << 6U)
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| (uint32)((uint32)0U << 5U)
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| (uint32)((uint32)0U << 4U)
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| (uint32)((uint32)0U << 3U)
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| (uint32)((uint32)0U << 2U)
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| (uint32)((uint32)0U << 1U)
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| (uint32)((uint32)0U << 0U);
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/* USER CODE BEGIN (4) */
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/* USER CODE END */
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}
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/** @fn uint32 esmError(void)
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* @brief Return Error status
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*
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* @return The error status
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*
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* Returns the error status.
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*/
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/* SourceId : ESM_SourceId_002 */
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/* DesignId : ESM_DesignId_002 */
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/* Requirements : HL_SR5 */
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uint32 esmError(void)
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{
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uint32 status;
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/* USER CODE BEGIN (5) */
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/* USER CODE END */
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status = esmREG->EPSR;
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/* USER CODE BEGIN (6) */
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/* USER CODE END */
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return status;
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}
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/** @fn void esmEnableError(uint64 channels)
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* @brief Enable Group 1 Channels Error Signals propagation
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*
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* @param[in] channels - Channel mask
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*
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* Enable Group 1 Channels Error Signals propagation to the error pin.
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*/
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/* SourceId : ESM_SourceId_003 */
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/* DesignId : ESM_DesignId_003 */
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/* Requirements : HL_SR6 */
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void esmEnableError(uint64 channels)
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{
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/* USER CODE BEGIN (7) */
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/* USER CODE END */
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esmREG->IEPSR4 = (uint32)((channels >> 32U) & 0xFFFFFFFFU);
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esmREG->EEPAPR1 = (uint32)(channels & 0xFFFFFFFFU);
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/* USER CODE BEGIN (8) */
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/* USER CODE END */
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}
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/** @fn void esmDisableError(uint64 channels)
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* @brief Disable Group 1 Channels Error Signals propagation
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*
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* @param[in] channels - Channel mask
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*
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* Disable Group 1 Channels Error Signals propagation to the error pin.
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*/
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/* SourceId : ESM_SourceId_004 */
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/* DesignId : ESM_DesignId_004 */
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/* Requirements : HL_SR7 */
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void esmDisableError(uint64 channels)
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{
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/* USER CODE BEGIN (9) */
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/* USER CODE END */
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esmREG->IEPCR4 = (uint32)((channels >> 32U) & 0xFFFFFFFFU);
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esmREG->DEPAPR1 = (uint32)(channels & 0xFFFFFFFFU);
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/* USER CODE BEGIN (10) */
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/* USER CODE END */
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}
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/** @fn void esmTriggerErrorPinReset(void)
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* @brief Trigger error pin reset and switch back to normal operation
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*
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* Trigger error pin reset and switch back to normal operation.
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*/
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/* SourceId : ESM_SourceId_005 */
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/* DesignId : ESM_DesignId_005 */
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/* Requirements : HL_SR8 */
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void esmTriggerErrorPinReset(void)
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{
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/* USER CODE BEGIN (11) */
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/* USER CODE END */
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esmREG->EKR = 5U;
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/* USER CODE BEGIN (12) */
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/* USER CODE END */
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}
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/** @fn void esmActivateNormalOperation(void)
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* @brief Activate normal operation
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*
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* Activates normal operation mode.
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*/
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/* SourceId : ESM_SourceId_006 */
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/* DesignId : ESM_DesignId_006 */
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/* Requirements : HL_SR9 */
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void esmActivateNormalOperation(void)
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{
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/* USER CODE BEGIN (13) */
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/* USER CODE END */
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esmREG->EKR = 0U;
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/* USER CODE BEGIN (14) */
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/* USER CODE END */
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}
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/** @fn void esmEnableInterrupt(uint64 channels)
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* @brief Enable Group 1 Channels Interrupts
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*
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* @param[in] channels - Channel mask
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*
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* Enable Group 1 Channels Interrupts.
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*/
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/* SourceId : ESM_SourceId_007 */
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/* DesignId : ESM_DesignId_007 */
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/* Requirements : HL_SR10 */
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void esmEnableInterrupt(uint64 channels)
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{
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/* USER CODE BEGIN (15) */
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/* USER CODE END */
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esmREG->IESR4 = (uint32)((channels >> 32U) & 0xFFFFFFFFU);
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esmREG->IESR1 = (uint32)(channels & 0xFFFFFFFFU);
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/* USER CODE BEGIN (16) */
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/* USER CODE END */
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}
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/** @fn void esmDisableInterrupt(uint64 channels)
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|
* @brief Disable Group 1 Channels Interrupts
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*
|
|
* @param[in] channels - Channel mask
|
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*
|
|
* Disable Group 1 Channels Interrupts.
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|
*/
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/* SourceId : ESM_SourceId_008 */
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/* DesignId : ESM_DesignId_008 */
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/* Requirements : HL_SR11 */
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|
void esmDisableInterrupt(uint64 channels)
|
|
{
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/* USER CODE BEGIN (17) */
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/* USER CODE END */
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esmREG->IECR4 = (uint32)((channels >> 32U) & 0xFFFFFFFFU);
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esmREG->IECR1 = (uint32)(channels & 0xFFFFFFFFU);
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/* USER CODE BEGIN (18) */
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/* USER CODE END */
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}
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/** @fn void esmSetInterruptLevel(uint64 channels, uint64 flags)
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* @brief Set Group 1 Channels Interrupt Levels
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*
|
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* @param[in] channels - Channel mask
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* @param[in] flags - Level mask: - 0: Low priority interrupt
|
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* - 1: High priority interrupt
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*
|
|
* Set Group 1 Channels Interrupts levels.
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|
*/
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/* SourceId : ESM_SourceId_009 */
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/* DesignId : ESM_DesignId_009 */
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/* Requirements : HL_SR12 */
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|
void esmSetInterruptLevel(uint64 channels, uint64 flags)
|
|
{
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|
/* USER CODE BEGIN (19) */
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/* USER CODE END */
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|
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esmREG->ILCR4 = (uint32)(((channels & (~flags)) >> 32U) & 0xFFFFFFFFU);
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esmREG->ILSR4 = (uint32)(((channels & flags) >> 32U) & 0xFFFFFFFFU);
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esmREG->ILCR1 = (uint32)((channels & (~flags)) & 0xFFFFFFFFU);
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esmREG->ILSR1 = (uint32)((channels & flags) & 0xFFFFFFFFU);
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/* USER CODE BEGIN (20) */
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/* USER CODE END */
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}
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/** @fn void esmClearStatus(uint32 group, uint64 channels)
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* @brief Clear Group error status
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*
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* @param[in] group - Error group
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* @param[in] channels - Channel mask
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*
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|
* Clear Group error status.
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|
*/
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|
/* SourceId : ESM_SourceId_010 */
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/* DesignId : ESM_DesignId_010 */
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/* Requirements : HL_SR13 */
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void esmClearStatus(uint32 group, uint64 channels)
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|
{
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/* USER CODE BEGIN (21) */
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|
/* USER CODE END */
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|
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|
esmREG->SR1[group] = (uint32)(channels & 0xFFFFFFFFU);
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if(group == 0U)
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{
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|
esmREG->SR4[group] = (uint32)((channels >> 32U) & 0xFFFFFFFFU);
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|
}
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|
|
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/* USER CODE BEGIN (22) */
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|
/* USER CODE END */
|
|
}
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|
|
|
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/** @fn void esmClearStatusBuffer(uint64 channels)
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|
* @brief Clear Group 2 error status buffer
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|
*
|
|
* @param[in] channels - Channel mask
|
|
*
|
|
* Clear Group 2 error status buffer.
|
|
*/
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|
/* SourceId : ESM_SourceId_011 */
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|
/* DesignId : ESM_DesignId_011 */
|
|
/* Requirements : HL_SR14 */
|
|
void esmClearStatusBuffer(uint64 channels)
|
|
{
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|
/* USER CODE BEGIN (23) */
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|
/* USER CODE END */
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|
|
|
esmREG->SSR2 = (uint32)(channels & 0xFFFFFFFFU);
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|
|
|
/* USER CODE BEGIN (24) */
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|
/* USER CODE END */
|
|
}
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|
|
|
|
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/** @fn void esmSetCounterPreloadValue(uint32 value)
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|
* @brief Set counter preload value
|
|
*
|
|
* @param[in] value - Counter preload value
|
|
*
|
|
* Set counter preload value.
|
|
*/
|
|
/* SourceId : ESM_SourceId_012 */
|
|
/* DesignId : ESM_DesignId_012 */
|
|
/* Requirements : HL_SR15 */
|
|
void esmSetCounterPreloadValue(uint32 value)
|
|
{
|
|
/* USER CODE BEGIN (25) */
|
|
/* USER CODE END */
|
|
|
|
esmREG->LTCPR = value & 0xC000U;
|
|
|
|
/* USER CODE BEGIN (26) */
|
|
/* USER CODE END */
|
|
}
|
|
|
|
|
|
/** @fn uint64 esmGetStatus(uint32 group, uint64 channels)
|
|
* @brief Return Error status
|
|
*
|
|
* @param[in] group - Error group
|
|
* @param[in] channels - Error Channels
|
|
*
|
|
* @return The channels status of selected group
|
|
*
|
|
* Returns the channels status of selected group.
|
|
*/
|
|
/* SourceId : ESM_SourceId_013 */
|
|
/* DesignId : ESM_DesignId_013 */
|
|
/* Requirements : HL_SR16 */
|
|
uint64 esmGetStatus(uint32 group, uint64 channels)
|
|
{
|
|
uint64 status;
|
|
uint32 ESM_ESTATUS4, ESM_ESTATUS1;
|
|
if(group == 0U)
|
|
{
|
|
ESM_ESTATUS4 = esmREG->SR4[group];
|
|
}
|
|
else
|
|
{
|
|
ESM_ESTATUS4 = 0U;
|
|
}
|
|
ESM_ESTATUS1 = esmREG->SR1[group];
|
|
|
|
/* USER CODE BEGIN (27) */
|
|
/* USER CODE END */
|
|
status = (((uint64)(ESM_ESTATUS4) << 32U) | (uint64)ESM_ESTATUS1) & channels;
|
|
|
|
/* USER CODE BEGIN (28) */
|
|
/* USER CODE END */
|
|
|
|
return status;
|
|
}
|
|
|
|
|
|
/** @fn uint64 esmGetStatusBuffer(uint64 channels)
|
|
* @brief Return Group 2 channel x Error status buffer
|
|
*
|
|
* @param[in] channels - Error Channels
|
|
*
|
|
* @return The channels status
|
|
*
|
|
* Returns the group 2 buffered status of selected channels.
|
|
*/
|
|
/* SourceId : ESM_SourceId_014 */
|
|
/* DesignId : ESM_DesignId_014 */
|
|
/* Requirements : HL_SR17 */
|
|
uint64 esmGetStatusBuffer(uint64 channels)
|
|
{
|
|
uint64 status;
|
|
|
|
/* USER CODE BEGIN (29) */
|
|
/* USER CODE END */
|
|
status = ((uint64)esmREG->SSR2) & channels;
|
|
|
|
/* USER CODE BEGIN (30) */
|
|
/* USER CODE END */
|
|
|
|
return status;
|
|
}
|
|
|
|
/** @fn esmSelfTestFlag_t esmEnterSelfTest(void)
|
|
* @brief Return ESM Self test status
|
|
*
|
|
* @return ESM Self test status
|
|
*
|
|
* Returns the ESM Self test status.
|
|
*/
|
|
/* SourceId : ESM_SourceId_015 */
|
|
/* DesignId : ESM_DesignId_015 */
|
|
/* Requirements : HL_SR19 */
|
|
esmSelfTestFlag_t esmEnterSelfTest(void)
|
|
{
|
|
esmSelfTestFlag_t status;
|
|
|
|
/* USER CODE BEGIN (31) */
|
|
/* USER CODE END */
|
|
|
|
uint32 errPinStat = esmREG->EPSR & 0x1U;
|
|
uint32 esmKeyReg = esmREG->EKR;
|
|
if((errPinStat == 0x0U) && (esmKeyReg == 0x0U))
|
|
{
|
|
status = esmSelfTest_NotStarted;
|
|
}
|
|
else
|
|
{
|
|
esmREG->EKR = 0xAU;
|
|
status = esmSelfTest_Active;
|
|
if((esmREG->EPSR & 0x1U) != 0x0U)
|
|
{
|
|
status = esmSelfTest_Failed;
|
|
}
|
|
esmREG->EKR = 0x5U;
|
|
}
|
|
|
|
/* USER CODE BEGIN (32) */
|
|
/* USER CODE END */
|
|
|
|
return status;
|
|
}
|
|
|
|
/** @fn esmSelfTestFlag_t esmSelfTestStatus(void)
|
|
* @brief Return ESM Self test status
|
|
*
|
|
* Returns the ESM Self test status.
|
|
*/
|
|
/* SourceId : ESM_SourceId_016 */
|
|
/* DesignId : ESM_DesignId_016 */
|
|
/* Requirements : HL_SR18 */
|
|
esmSelfTestFlag_t esmSelfTestStatus(void)
|
|
{
|
|
esmSelfTestFlag_t status;
|
|
|
|
/* USER CODE BEGIN (33) */
|
|
/* USER CODE END */
|
|
|
|
if((esmREG->EPSR & 0x1U) == 0x0U)
|
|
{
|
|
if(esmREG->EKR == 0x5U)
|
|
{
|
|
status = esmSelfTest_Active;
|
|
}
|
|
else
|
|
{
|
|
status = esmSelfTest_Failed;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
status = esmSelfTest_Passed;
|
|
}
|
|
|
|
/* USER CODE BEGIN (34) */
|
|
/* USER CODE END */
|
|
|
|
return status;
|
|
}
|
|
|
|
/** @fn void esmGetConfigValue(esm_config_reg_t *config_reg, config_value_type_t type)
|
|
* @brief Get the initial or current values of the configuration registers
|
|
*
|
|
* @param[in] *config_reg: pointer to the struct to which the initial or current
|
|
* value of the configuration registers need to be stored
|
|
* @param[in] type: whether initial or current value of the configuration registers need to be stored
|
|
* - InitialValue: initial value of the configuration registers will be stored
|
|
* in the struct pointed by config_reg
|
|
* - CurrentValue: initial value of the configuration registers will be stored
|
|
* in the struct pointed by config_reg
|
|
*
|
|
* This function will copy the initial or current value (depending on the parameter 'type')
|
|
* of the configuration registers to the struct pointed by config_reg
|
|
*
|
|
*/
|
|
/* SourceId : ESM_SourceId_017 */
|
|
/* DesignId : ESM_DesignId_017 */
|
|
/* Requirements : HL_SR20, HL_SR24 */
|
|
void esmGetConfigValue(esm_config_reg_t *config_reg, config_value_type_t type)
|
|
{
|
|
if (type == InitialValue)
|
|
{
|
|
config_reg->CONFIG_EEPAPR1 = ESM_EEPAPR1_CONFIGVALUE;
|
|
config_reg->CONFIG_IESR1 = ESM_IESR1_CONFIGVALUE;
|
|
config_reg->CONFIG_ILSR1 = ESM_ILSR1_CONFIGVALUE;
|
|
config_reg->CONFIG_LTCPR = ESM_LTCPR_CONFIGVALUE;
|
|
config_reg->CONFIG_EKR = ESM_EKR_CONFIGVALUE;
|
|
config_reg->CONFIG_IEPSR4 = ESM_IEPSR4_CONFIGVALUE;
|
|
config_reg->CONFIG_IESR4 = ESM_IESR4_CONFIGVALUE;
|
|
config_reg->CONFIG_ILSR4 = ESM_ILSR4_CONFIGVALUE;
|
|
}
|
|
else
|
|
{
|
|
/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
|
|
config_reg->CONFIG_EEPAPR1 = esmREG->EEPAPR1;
|
|
config_reg->CONFIG_IESR1 = esmREG->IESR1;
|
|
config_reg->CONFIG_ILSR1 = esmREG->ILSR1;
|
|
config_reg->CONFIG_LTCPR = esmREG->LTCPR;
|
|
config_reg->CONFIG_EKR = esmREG->EKR;
|
|
config_reg->CONFIG_IEPSR4 = esmREG->IEPSR4;
|
|
config_reg->CONFIG_IESR4 = esmREG->IESR4;
|
|
config_reg->CONFIG_ILSR4 = esmREG->ILSR4;
|
|
}
|
|
}
|
|
|
|
/* USER CODE BEGIN (35) */
|
|
/* USER CODE END */
|
|
|
|
/** @fn void esmHighInterrupt(void)
|
|
* @brief High Level Interrupt for ESM
|
|
*/
|
|
#pragma CODE_STATE(esmHighInterrupt, 32)
|
|
#pragma INTERRUPT(esmHighInterrupt, FIQ)
|
|
/* SourceId : ESM_SourceId_018 */
|
|
/* DesignId : ESM_DesignId_018 */
|
|
/* Requirements : HL_SR21, HL_SR22 */
|
|
void esmHighInterrupt(void)
|
|
{
|
|
uint32 vec = esmREG->IOFFHR - 1U;
|
|
|
|
/* USER CODE BEGIN (36) */
|
|
/* USER CODE END */
|
|
|
|
if (vec < 32U)
|
|
{
|
|
esmREG->SR1[0U] = (uint32)1U << vec;
|
|
esmGroup1Notification(vec);
|
|
}
|
|
else if (vec < 64U)
|
|
{
|
|
esmREG->SR1[1U] = (uint32)1U << (vec-32U);
|
|
esmGroup2Notification(vec-32U);
|
|
}
|
|
else if (vec < 96U)
|
|
{
|
|
esmREG->SR4[0U] = (uint32)1U << (vec-64U);
|
|
esmGroup1Notification(vec-32U);
|
|
}
|
|
else
|
|
{
|
|
esmREG->SR4[0U] = 0xFFFFFFFFU;
|
|
esmREG->SR1[1U] = 0xFFFFFFFFU;
|
|
esmREG->SR1[0U] = 0xFFFFFFFFU;
|
|
}
|
|
|
|
/* USER CODE BEGIN (37) */
|
|
/* USER CODE END */
|
|
}
|
|
|
|
|
|
/* USER CODE BEGIN (41) */
|
|
/* USER CODE END */
|