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330 lines
12 KiB
C
330 lines
12 KiB
C
/***************************************************************************//**
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* @file em_bus.h
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* @brief RAM and peripheral bit-field set and clear API
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* @version 4.3.0
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*******************************************************************************
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* @section License
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* <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
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*******************************************************************************
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*
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* Permission is granted to anyone to use this software for any purpose,
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* including commercial applications, and to alter it and redistribute it
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* freely, subject to the following restrictions:
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*
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* 1. The origin of this software must not be misrepresented; you must not
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* claim that you wrote the original software.
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* 2. Altered source versions must be plainly marked as such, and must not be
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* misrepresented as being the original software.
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* 3. This notice may not be removed or altered from any source distribution.
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*
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* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
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* obligation to support this Software. Silicon Labs is providing the
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* Software "AS IS", with no express or implied warranties of any kind,
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* including, but not limited to, any implied warranties of merchantability
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* or fitness for any particular purpose or warranties against infringement
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* of any proprietary rights of a third party.
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*
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* Silicon Labs will not be liable for any consequential, incidental, or
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* special damages, or any other relief, or for any claim by any third party,
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* arising from your use of this Software.
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*
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******************************************************************************/
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#ifndef EM_BUS__
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#define EM_BUS__
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#include "em_device.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************************************************************//**
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* @addtogroup emlib
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* @{
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******************************************************************************/
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/***************************************************************************//**
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* @addtogroup BUS
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* @brief BUS RAM and register bit/field read/write API
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* @details
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* API to perform bitbanded and masked accesses to SRAM and peripheral memory.
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* @{
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******************************************************************************/
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/***************************************************************************//**
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* @brief
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* Perform a single-bit write operation on a 32-bit word in RAM
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*
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* @details
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* This function uses Cortex-M bit-banding hardware to perform an atomic
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* read-modify-write operation on a single bit write on a 32-bit word in RAM.
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* Please refer to the reference manual for further details about bit-banding.
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*
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* @note
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* This function is atomic on Cortex-M cores with bit-banding support. Bit-
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* banding is a multicycle read-modify-write bus operation. RAM bit-banding is
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* performed using the memory alias region at BITBAND_RAM_BASE.
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*
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* @param[in] addr Address of 32-bit word in RAM
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*
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* @param[in] bit Bit position to write, 0-31
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*
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* @param[in] val Value to set bit to, 0 or 1
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******************************************************************************/
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__STATIC_INLINE void BUS_RamBitWrite(volatile uint32_t *addr,
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unsigned int bit,
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unsigned int val)
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{
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#if defined( BITBAND_RAM_BASE )
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uint32_t aliasAddr =
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BITBAND_RAM_BASE + (((uint32_t)addr - SRAM_BASE) * 32) + (bit * 4);
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*(volatile uint32_t *)aliasAddr = (uint32_t)val;
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#else
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uint32_t tmp = *addr;
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/* Make sure val is not more than 1, because we only want to set one bit. */
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*addr = (tmp & ~(1 << bit)) | ((val & 1) << bit);
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#endif
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}
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/***************************************************************************//**
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* @brief
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* Perform a single-bit read operation on a 32-bit word in RAM
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*
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* @details
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* This function uses Cortex-M bit-banding hardware to perform an atomic
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* read operation on a single register bit. Please refer to the
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* reference manual for further details about bit-banding.
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*
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* @note
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* This function is atomic on Cortex-M cores with bit-banding support.
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* RAM bit-banding is performed using the memory alias region
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* at BITBAND_RAM_BASE.
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*
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* @param[in] addr RAM address
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*
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* @param[in] bit Bit position to read, 0-31
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*
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* @return
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* The requested bit shifted to bit position 0 in the return value
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******************************************************************************/
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__STATIC_INLINE unsigned int BUS_RamBitRead(volatile const uint32_t *addr,
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unsigned int bit)
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{
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#if defined( BITBAND_RAM_BASE )
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uint32_t aliasAddr =
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BITBAND_RAM_BASE + (((uint32_t)addr - SRAM_BASE) * 32) + (bit * 4);
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return *(volatile uint32_t *)aliasAddr;
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#else
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return ((*addr) >> bit) & 1;
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#endif
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}
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/***************************************************************************//**
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* @brief
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* Perform a single-bit write operation on a peripheral register
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*
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* @details
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* This function uses Cortex-M bit-banding hardware to perform an atomic
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* read-modify-write operation on a single register bit. Please refer to the
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* reference manual for further details about bit-banding.
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*
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* @note
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* This function is atomic on Cortex-M cores with bit-banding support. Bit-
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* banding is a multicycle read-modify-write bus operation. Peripheral register
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* bit-banding is performed using the memory alias region at BITBAND_PER_BASE.
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*
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* @param[in] addr Peripheral register address
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*
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* @param[in] bit Bit position to write, 0-31
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*
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* @param[in] val Value to set bit to, 0 or 1
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******************************************************************************/
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__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr,
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unsigned int bit,
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unsigned int val)
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{
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#if defined( BITBAND_PER_BASE )
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uint32_t aliasAddr =
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BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) * 32) + (bit * 4);
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*(volatile uint32_t *)aliasAddr = (uint32_t)val;
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#else
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uint32_t tmp = *addr;
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/* Make sure val is not more than 1, because we only want to set one bit. */
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*addr = (tmp & ~(1 << bit)) | ((val & 1) << bit);
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#endif
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}
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/***************************************************************************//**
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* @brief
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* Perform a single-bit read operation on a peripheral register
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*
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* @details
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* This function uses Cortex-M bit-banding hardware to perform an atomic
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* read operation on a single register bit. Please refer to the
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* reference manual for further details about bit-banding.
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*
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* @note
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* This function is atomic on Cortex-M cores with bit-banding support.
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* Peripheral register bit-banding is performed using the memory alias
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* region at BITBAND_PER_BASE.
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*
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* @param[in] addr Peripheral register address
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*
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* @param[in] bit Bit position to read, 0-31
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*
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* @return
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* The requested bit shifted to bit position 0 in the return value
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******************************************************************************/
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__STATIC_INLINE unsigned int BUS_RegBitRead(volatile const uint32_t *addr,
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unsigned int bit)
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{
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#if defined( BITBAND_PER_BASE )
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uint32_t aliasAddr =
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BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) * 32) + (bit * 4);
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return *(volatile uint32_t *)aliasAddr;
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#else
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return ((*addr) >> bit) & 1;
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#endif
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}
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/***************************************************************************//**
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* @brief
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* Perform a masked set operation on peripheral register address.
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*
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* @details
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* Peripheral register masked set provides a single-cycle and atomic set
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* operation of a bit-mask in a peripheral register. All 1's in the mask are
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* set to 1 in the register. All 0's in the mask are not changed in the
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* register.
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* RAMs and special peripherals are not supported. Please refer to the
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* reference manual for further details about peripheral register field set.
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*
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* @note
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* This function is single-cycle and atomic on cores with peripheral bit set
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* and clear support. It uses the memory alias region at PER_BITSET_MEM_BASE.
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*
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* @param[in] addr Peripheral register address
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*
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* @param[in] mask Mask to set
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******************************************************************************/
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__STATIC_INLINE void BUS_RegMaskedSet(volatile uint32_t *addr,
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uint32_t mask)
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{
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#if defined( PER_BITSET_MEM_BASE )
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uint32_t aliasAddr = PER_BITSET_MEM_BASE + ((uint32_t)addr - PER_MEM_BASE);
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*(volatile uint32_t *)aliasAddr = mask;
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#else
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*addr |= mask;
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#endif
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}
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/***************************************************************************//**
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* @brief
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* Perform a masked clear operation on peripheral register address.
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*
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* @details
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* Peripheral register masked clear provides a single-cycle and atomic clear
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* operation of a bit-mask in a peripheral register. All 1's in the mask are
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* set to 0 in the register.
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* All 0's in the mask are not changed in the register.
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* RAMs and special peripherals are not supported. Please refer to the
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* reference manual for further details about peripheral register field clear.
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*
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* @note
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* This function is single-cycle and atomic on cores with peripheral bit set
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* and clear support. It uses the memory alias region at PER_BITCLR_MEM_BASE.
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*
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* @param[in] addr Peripheral register address
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*
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* @param[in] mask Mask to clear
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******************************************************************************/
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__STATIC_INLINE void BUS_RegMaskedClear(volatile uint32_t *addr,
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uint32_t mask)
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{
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#if defined( PER_BITCLR_MEM_BASE )
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uint32_t aliasAddr = PER_BITCLR_MEM_BASE + ((uint32_t)addr - PER_MEM_BASE);
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*(volatile uint32_t *)aliasAddr = mask;
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#else
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*addr &= ~mask;
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#endif
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}
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/***************************************************************************//**
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* @brief
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* Perform peripheral register masked clear and value write.
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*
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* @details
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* This function first clears the mask in the peripheral register, then
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* writes the value. Typically the mask is a bit-field in the register, and
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* the value val is within the mask.
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*
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* @note
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* This operation is not atomic. Note that the mask is first set to 0 before
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* the val is set.
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*
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* @param[in] addr Peripheral register address
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*
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* @param[in] mask Peripheral register mask
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*
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* @param[in] val Peripheral register value. The value must be shifted to the
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correct bit position in the register.
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******************************************************************************/
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__STATIC_INLINE void BUS_RegMaskedWrite(volatile uint32_t *addr,
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uint32_t mask,
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uint32_t val)
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{
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#if defined( PER_BITCLR_MEM_BASE )
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BUS_RegMaskedClear(addr, mask);
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BUS_RegMaskedSet(addr, val);
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#else
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*addr = (*addr & ~mask) | val;
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#endif
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}
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/***************************************************************************//**
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* @brief
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* Perform a peripheral register masked read
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*
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* @details
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* Read an unshifted and masked value from a peripheral register.
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*
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* @note
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* This operation is not hardware accelerated.
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*
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* @param[in] addr Peripheral register address
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*
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* @param[in] mask Peripheral register mask
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*
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* @return
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* Unshifted and masked register value
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******************************************************************************/
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__STATIC_INLINE uint32_t BUS_RegMaskedRead(volatile const uint32_t *addr,
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uint32_t mask)
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{
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return *addr & mask;
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}
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/** @} (end addtogroup BUS) */
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/** @} (end addtogroup emlib) */
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#ifdef __cplusplus
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}
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#endif
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#endif /* EM_BUS__ */
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