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https://github.com/QuantumLeaps/qpcpp.git
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242 lines
9.0 KiB
C++
242 lines
9.0 KiB
C++
/// @file
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/// @brief QUTEST port for the EK-TM4C123GXL board
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/// @ingroup qs
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/// @cond
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///***************************************************************************
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/// Last updated for version 6.3.8
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/// Last updated on 2019-01-24
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///
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/// Q u a n t u m L e a P s
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/// ------------------------
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/// Modern Embedded Software
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///
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/// Copyright (C) 2005-2019 Quantum Leaps, LLC. All rights reserved.
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///
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/// This program is open source software: you can redistribute it and/or
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/// modify it under the terms of the GNU General Public License as published
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/// by the Free Software Foundation, either version 3 of the License, or
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/// (at your option) any later version.
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///
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/// Alternatively, this program may be distributed and modified under the
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/// terms of Quantum Leaps commercial licenses, which expressly supersede
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/// the GNU General Public License and are specifically designed for
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/// licensees interested in retaining the proprietary status of their code.
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///
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/// This program is distributed in the hope that it will be useful,
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/// but WITHOUT ANY WARRANTY; without even the implied warranty of
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/// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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/// GNU General Public License for more details.
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///
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/// You should have received a copy of the GNU General Public License
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/// along with this program. If not, see <http://www.gnu.org/licenses/>.
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///
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/// Contact information:
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/// https://state-machine.com
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/// mailto:info@state-machine.com
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///***************************************************************************
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/// @endcond
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#include "qpcpp.h"
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#include "TM4C123GH6PM.h" // the device specific header (TI)
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#include "rom.h" // the built-in ROM functions (TI)
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#include "sysctl.h" // system control driver (TI)
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#include "gpio.h" // GPIO driver (TI)
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// add other drivers if necessary...
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//Q_DEFINE_THIS_MODULE("qutest_port")
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using namespace QP;
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// !!!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
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// Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
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// DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!
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//
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enum KernelUnawareISRs { // see NOTE00
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UART0_PRIO,
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// ...
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MAX_KERNEL_UNAWARE_CMSIS_PRI // keep always last
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};
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// "kernel-unaware" interrupts can't overlap "kernel-aware" interrupts
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//Q_ASSERT_COMPILE(MAX_KERNEL_UNAWARE_CMSIS_PRI <= QF_AWARE_ISR_CMSIS_PRI);
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// ISRs defined in this BSP --------------------------------------------------
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extern "C" void UART0_IRQHandler(void); // prototype
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// Local-scope objects -------------------------------------------------------
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#define LED_RED (1U << 1)
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#define LED_BLUE (1U << 2)
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#define LED_GREEN (1U << 3)
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#define BTN_SW1 (1U << 4)
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#define BTN_SW2 (1U << 0)
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#define UART_BAUD_RATE 115200U
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#define UART_FR_TXFE (1U << 7)
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#define UART_FR_RXFE (1U << 4)
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#define UART_TXFIFO_DEPTH 16U
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//............................................................................
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extern "C" {
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// ISR for receiving bytes from the QSPY Back-End
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// NOTE: This ISR is "QF-unaware" meaning that it does not interact with
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// the QF/QK and is not disabled. Such ISRs don't need to call QK_ISR_ENTRY/
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// QK_ISR_EXIT and they cannot post or publish events.
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//
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void UART0_IRQHandler(void) {
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// while RX FIFO NOT empty
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while ((UART0->FR & UART_FR_RXFE) == 0) {
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uint32_t b = UART0->DR;
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QP::QS::rxPut(b);
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}
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}
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} // extern "C"
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// QS callbacks ==============================================================
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bool QS::onStartup(void const *arg) {
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static uint8_t qsTxBuf[2*1024]; // buffer for QS transmit channel
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static uint8_t qsRxBuf[100]; // buffer for QS receive channel
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uint32_t tmp;
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initBuf (qsTxBuf, sizeof(qsTxBuf));
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rxInitBuf(qsRxBuf, sizeof(qsRxBuf));
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// NOTE: SystemInit() already called from the startup code
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// but SystemCoreClock needs to be updated
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//
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SystemCoreClockUpdate();
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// configure the FPU usage by choosing one of the options... */
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#if 0
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// OPTION 1:
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// Use the automatic FPU state preservation and the FPU lazy stacking.
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//
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// NOTE:
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// Use the following setting when FPU is used in more than one task or
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// in any ISRs. This setting is the safest and recommended, but requires
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// extra stack space and CPU cycles.
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//
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FPU->FPCCR |= (1U << FPU_FPCCR_ASPEN_Pos) | (1U << FPU_FPCCR_LSPEN_Pos);
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#else
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// OPTION 2:
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// Do NOT to use the automatic FPU state preservation and
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// do NOT to use the FPU lazy stacking.
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//
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// NOTE:
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// Use the following setting when FPU is used in ONE task only and not
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// in any ISR. This setting is very efficient, but if more than one task
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// (or ISR) start using the FPU, this can lead to corruption of the
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// FPU registers. This option should be used with CAUTION.
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//
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FPU->FPCCR &= ~((1U << FPU_FPCCR_ASPEN_Pos)
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| (1U << FPU_FPCCR_LSPEN_Pos));
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#endif // FPU
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// enable clock for to the peripherals used by this application...
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SYSCTL->RCGCGPIO |= (1U << 5); // enable Run mode for GPIOF
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// configure the LEDs and push buttons
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GPIOF->DIR |= (LED_RED | LED_GREEN | LED_BLUE);// set direction: output
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GPIOF->DEN |= (LED_RED | LED_GREEN | LED_BLUE); // digital enable
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GPIOF->DATA_Bits[LED_RED] = 0U; // turn the LED off
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GPIOF->DATA_Bits[LED_GREEN] = 0U; // turn the LED off
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GPIOF->DATA_Bits[LED_BLUE] = 0U; // turn the LED off
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// configure the Buttons
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GPIOF->DIR &= ~(BTN_SW1 | BTN_SW2); // set direction: input
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ROM_GPIOPadConfigSet(GPIOF_BASE, (BTN_SW1 | BTN_SW2),
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GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU);
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// enable clock for UART0 and GPIOA (used by UART0 pins)
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SYSCTL->RCGCUART |= (1U << 0); // enable Run mode for UART0
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SYSCTL->RCGCGPIO |= (1U << 0); // enable Run mode for GPIOA
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// configure UART0 pins for UART operation
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tmp = (1U << 0) | (1U << 1);
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GPIOA->DIR &= ~tmp;
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GPIOA->SLR &= ~tmp;
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GPIOA->ODR &= ~tmp;
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GPIOA->PUR &= ~tmp;
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GPIOA->PDR &= ~tmp;
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GPIOA->AMSEL &= ~tmp; // disable analog function on the pins
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GPIOA->AFSEL |= tmp; // enable ALT function on the pins
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GPIOA->DEN |= tmp; // enable digital I/O on the pins
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GPIOA->PCTL &= ~0x00U;
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GPIOA->PCTL |= 0x11U;
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// configure the UART for the desired baud rate, 8-N-1 operation
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tmp = (((SystemCoreClock * 8U) / UART_BAUD_RATE) + 1U) / 2U;
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UART0->IBRD = tmp / 64U;
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UART0->FBRD = tmp % 64U;
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UART0->LCRH = (0x3U << 5); // configure 8-N-1 operation
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UART0->LCRH |= (0x1U << 4); // enable FIFOs
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UART0->CTL = (1U << 0) // UART enable
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| (1U << 8) // UART TX enable
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| (1U << 9); // UART RX enable
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// configure UART interrupts (for the RX channel)
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UART0->IM |= (1U << 4) | (1U << 6); // enable RX and RX-TO interrupt
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UART0->IFLS |= (0x2U << 2); // interrupt on RX FIFO half-full
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// enable the UART RX interrupt...
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NVIC_SetPriorityGrouping(0U);
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NVIC_SetPriority(UART0_IRQn, UART0_PRIO);
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NVIC_EnableIRQ(UART0_IRQn); // UART0 interrupt used for QS-RX
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return true; // return success
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}
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//............................................................................
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void QS::onCleanup(void) {
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}
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//............................................................................
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void QS::onFlush(void) {
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uint16_t fifo = UART_TXFIFO_DEPTH; // Tx FIFO depth
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uint8_t const *block;
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while ((block = getBlock(&fifo)) != (uint8_t *)0) {
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GPIOF->DATA_Bits[LED_GREEN] = LED_GREEN;
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// busy-wait as long as TX FIFO has data to transmit
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while ((UART0->FR & UART_FR_TXFE) == 0) {
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}
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while (fifo-- != 0) { // any bytes in the block?
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UART0->DR = *block++; // put into the TX FIFO
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}
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fifo = UART_TXFIFO_DEPTH; // re-load the Tx FIFO depth
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GPIOF->DATA_Bits[LED_GREEN] = 0U;
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}
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}
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//............................................................................
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// callback function to reset the target (to be implemented in the BSP)
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void QS::onReset(void) {
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NVIC_SystemReset();
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}
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//............................................................................
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void QS::onTestLoop() {
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rxPriv_.inTestLoop = true;
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while (rxPriv_.inTestLoop) {
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// turn the LED1 on and off (glow)
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GPIOF->DATA_Bits[LED_BLUE] = LED_BLUE; // turn the Blue LED on
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GPIOF->DATA_Bits[LED_BLUE] = 0U; // turn the Blue LED off
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rxParse(); // parse all the received bytes
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if ((UART0->FR & UART_FR_TXFE) != 0U) { // TX done?
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uint16_t fifo = UART_TXFIFO_DEPTH; // max bytes we can accept
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uint8_t const *block;
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block = getBlock(&fifo); // try to get next block to transmit
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while (fifo-- != 0) { // any bytes in the block?
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UART0->DR = *block++; // put into the FIFO
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}
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}
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}
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// set inTestLoop to true in case calls to QS_onTestLoop() nest,
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// which can happen through the calls to QS_TEST_PAUSE().
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rxPriv_.inTestLoop = true;
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}
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