mirror of
https://github.com/QuantumLeaps/qpcpp.git
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493 lines
18 KiB
C++
493 lines
18 KiB
C++
///***************************************************************************
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// Product: DPP example, EK-TM4C123GXL board, cooperative QV kernel
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// Last updated for version 5.6.4
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// Last updated on 201-06-06
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//
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// Q u a n t u m L e a P s
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// ---------------------------
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// innovating embedded systems
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//
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// Copyright (C) Quantum Leaps, LLC. All rights reserved.
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//
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// This program is open source software: you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// Alternatively, this program may be distributed and modified under the
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// terms of Quantum Leaps commercial licenses, which expressly supersede
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// the GNU General Public License and are specifically designed for
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// licensees interested in retaining the proprietary status of their code.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// Contact information:
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// http://www.state-machine.com
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// mailto:info@state-machine.com
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//****************************************************************************
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#include "qpcpp.h"
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#include "dpp.h"
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#include "bsp.h"
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#include "TM4C123GH6PM.h" // the device specific header (TI)
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#include "rom.h" // the built-in ROM functions (TI)
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#include "sysctl.h" // system control driver (TI)
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#include "gpio.h" // GPIO driver (TI)
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// add other drivers if necessary...
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// namespace DPP *************************************************************
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namespace DPP {
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Q_DEFINE_THIS_FILE
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// !!!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
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// Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
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// DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!
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//
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enum KernelUnawareISRs { // see NOTE00
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UART0_PRIO,
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// ...
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MAX_KERNEL_UNAWARE_CMSIS_PRI // keep always last
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};
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// "kernel-unaware" interrupts can't overlap "kernel-aware" interrupts
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Q_ASSERT_COMPILE(MAX_KERNEL_UNAWARE_CMSIS_PRI <= QF_AWARE_ISR_CMSIS_PRI);
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enum KernelAwareISRs {
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GPIOA_PRIO = QF_AWARE_ISR_CMSIS_PRI, // see NOTE00
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SYSTICK_PRIO,
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// ...
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MAX_KERNEL_AWARE_CMSIS_PRI // keep always last
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};
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// "kernel-aware" interrupts should not overlap the PendSV priority
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Q_ASSERT_COMPILE(MAX_KERNEL_AWARE_CMSIS_PRI <= (0xFF >>(8-__NVIC_PRIO_BITS)));
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// Local-scope objects -------------------------------------------------------
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#define LED_RED (1U << 1)
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#define LED_GREEN (1U << 3)
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#define LED_BLUE (1U << 2)
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#define BTN_SW1 (1U << 4)
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#define BTN_SW2 (1U << 0)
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static uint32_t l_rnd; // random seed
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#ifdef Q_SPY
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QP::QSTimeCtr QS_tickTime_;
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QP::QSTimeCtr QS_tickPeriod_;
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static uint8_t l_SysTick_Handler;
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static uint8_t l_GPIOPortA_IRQHandler;
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#define UART_BAUD_RATE 115200U
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#define UART_FR_TXFE (1U << 7)
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#define UART_FR_RXFE (1U << 4)
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#define UART_TXFIFO_DEPTH 16U
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enum AppRecords { // application-specific trace records
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PHILO_STAT = QP::QS_USER,
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COMMAND_STAT
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};
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#endif
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// ISRs used in this project =================================================
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extern "C" {
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//............................................................................
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void SysTick_Handler(void); // prototype
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void SysTick_Handler(void) {
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// state of the button debouncing, see below
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static struct ButtonsDebouncing {
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uint32_t depressed;
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uint32_t previous;
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} buttons = { ~0U, ~0U };
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uint32_t current;
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uint32_t tmp;
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#ifdef Q_SPY
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{
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tmp = SysTick->CTRL; // clear SysTick_CTRL_COUNTFLAG
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QS_tickTime_ += QS_tickPeriod_; // account for the clock rollover
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}
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#endif
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QP::QF::TICK_X(0U, &l_SysTick_Handler); // process time events for rate 0
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// Perform the debouncing of buttons. The algorithm for debouncing
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// adapted from the book "Embedded Systems Dictionary" by Jack Ganssle
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// and Michael Barr, page 71.
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//
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current = ~GPIOF->DATA_Bits[BTN_SW1 | BTN_SW2]; // read SW1 and SW2
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tmp = buttons.depressed; // save the debounced depressed buttons
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buttons.depressed |= (buttons.previous & current); // set depressed
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buttons.depressed &= (buttons.previous | current); // clear released
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buttons.previous = current; // update the history
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tmp ^= buttons.depressed; // changed debounced depressed
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if ((tmp & BTN_SW1) != 0U) { // debounced SW1 state changed?
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if ((buttons.depressed & BTN_SW1) != 0U) { // is SW1 depressed?
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static QP::QEvt const pauseEvt = { DPP::PAUSE_SIG, 0U, 0U};
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QP::QF::PUBLISH(&pauseEvt, &l_SysTick_Handler);
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}
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else { // the button is released
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static QP::QEvt const serveEvt = { DPP::SERVE_SIG, 0U, 0U};
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QP::QF::PUBLISH(&serveEvt, &l_SysTick_Handler);
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}
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}
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}
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//............................................................................
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void GPIOPortA_IRQHandler(void); // prototype
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void GPIOPortA_IRQHandler(void) {
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// for testing..
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DPP::AO_Table->POST(Q_NEW(QP::QEvt, DPP::MAX_PUB_SIG),
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&l_GPIOPortA_IRQHandler);
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}
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//............................................................................
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void UART0_IRQHandler(void); // prototype
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#ifdef Q_SPY
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// ISR for receiving bytes from the QSPY Back-End
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// NOTE: This ISR is "QF-unaware" meaning that it does not interact with
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// the QF/QK and is not disabled. Such ISRs don't need to call QK_ISR_ENTRY/
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// QK_ISR_EXIT and they cannot post or publish events.
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//
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void UART0_IRQHandler(void) {
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uint32_t status = UART0->RIS; // get the raw interrupt status
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UART0->ICR = status; // clear the asserted interrupts
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while ((UART0->FR & UART_FR_RXFE) == 0) { // while RX FIFO NOT empty
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uint8_t b = static_cast<uint8_t>(UART0->DR);
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QP::QS::rxPut(b);
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}
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}
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#else
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void UART0_IRQHandler(void) {}
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#endif // Q_SPY
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} // extern "C"
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// BSP functions =============================================================
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void BSP::init(void) {
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// NOTE: SystemInit() already called from the startup code
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// but SystemCoreClock needs to be updated
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//
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SystemCoreClockUpdate();
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// configure the FPU usage by choosing one of the options...
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// Do NOT to use the automatic FPU state preservation and
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// do NOT to use the FPU lazy stacking.
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//
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// NOTE:
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// Use the following setting when FPU is used in ONE task only and not
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// in any ISR. This option should be used with CAUTION.
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//
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FPU->FPCCR &= ~((1U << FPU_FPCCR_ASPEN_Pos) | (1U << FPU_FPCCR_LSPEN_Pos));
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// enable clock for to the peripherals used by this application...
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SYSCTL->RCGCGPIO |= (1U << 5); // enable Run mode for GPIOF
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// configure the LEDs and push buttons
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GPIOF->DIR |= (LED_RED | LED_GREEN | LED_BLUE); // set direction: output
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GPIOF->DEN |= (LED_RED | LED_GREEN | LED_BLUE); // digital enable
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GPIOF->DATA_Bits[LED_RED] = 0U; // turn the LED off
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GPIOF->DATA_Bits[LED_GREEN] = 0U; // turn the LED off
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GPIOF->DATA_Bits[LED_BLUE] = 0U; // turn the LED off
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// configure the Buttons
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GPIOF->DIR &= ~(BTN_SW1 | BTN_SW2); // set direction: input
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ROM_GPIOPadConfigSet(GPIOF_BASE, (BTN_SW1 | BTN_SW2),
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GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU);
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BSP::randomSeed(1234U);
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if (!QS_INIT((void *)0)) { // initialize the QS software tracing
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Q_ERROR();
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}
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QS_OBJ_DICTIONARY(&l_SysTick_Handler);
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QS_OBJ_DICTIONARY(&l_GPIOPortA_IRQHandler);
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QS_USR_DICTIONARY(PHILO_STAT);
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QS_USR_DICTIONARY(COMMAND_STAT);
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}
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//............................................................................
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void BSP::displayPhilStat(uint8_t n, char const *stat) {
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GPIOF->DATA_Bits[LED_RED] = ((stat[0] == 'h') ? 0xFFU : 0U);
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GPIOF->DATA_Bits[LED_GREEN] = ((stat[0] == 'e') ? 0xFFU : 0U);
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QS_BEGIN(PHILO_STAT, AO_Philo[n]) // application-specific record begin
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QS_U8(1, n); // Philosopher number
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QS_STR(stat); // Philosopher status
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QS_END()
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}
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//............................................................................
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void BSP::displayPaused(uint8_t paused) {
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GPIOF->DATA_Bits[LED_RED] = ((paused != 0U) ? 0xFFU : 0U);
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}
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//............................................................................
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uint32_t BSP::random(void) { // a very cheap pseudo-random-number generator
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// The flating point code is to exercise the FPU
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float volatile x = 3.1415926F;
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x = x + 2.7182818F;
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// "Super-Duper" Linear Congruential Generator (LCG)
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// LCG(2^32, 3*7*11*13*23, 0, seed)
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//
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uint32_t rnd = l_rnd * (3U*7U*11U*13U*23U);
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l_rnd = rnd; // set for the next time
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return (rnd >> 8);
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}
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//............................................................................
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void BSP::randomSeed(uint32_t seed) {
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l_rnd = seed;
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}
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//............................................................................
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void BSP::ledOn(void) {
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GPIOF->DATA_Bits[LED_RED] = 0xFFU;
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}
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//............................................................................
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void BSP::ledOff(void) {
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GPIOF->DATA_Bits[LED_RED] = 0x00U;
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}
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//............................................................................
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void BSP::terminate(int16_t result) {
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(void)result;
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}
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} // namespace DPP
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// namespace QP **************************************************************
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namespace QP {
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// QF callbacks ==============================================================
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void QF::onStartup(void) {
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// set up the SysTick timer to fire at BSP::TICKS_PER_SEC rate
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SysTick_Config(SystemCoreClock / DPP::BSP::TICKS_PER_SEC);
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// assing all priority bits for preemption-prio. and none to sub-prio.
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NVIC_SetPriorityGrouping(0U);
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// set priorities of ALL ISRs used in the system, see NOTE00
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//
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// !!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
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// Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
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// DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!
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//
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NVIC_SetPriority(UART0_IRQn, DPP::UART0_PRIO);
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NVIC_SetPriority(SysTick_IRQn, DPP::SYSTICK_PRIO);
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NVIC_SetPriority(GPIOA_IRQn, DPP::GPIOA_PRIO);
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// ...
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// enable IRQs...
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NVIC_EnableIRQ(GPIOA_IRQn);
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#ifdef Q_SPY
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NVIC_EnableIRQ(UART0_IRQn); // UART0 interrupt used for QS-RX
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#endif
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}
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//............................................................................
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void QF::onCleanup(void) {
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}
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//............................................................................
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void QV::onIdle(void) { // called with interrupts disabled, see NOTE01
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// toggle the User LED on and then off, see NOTE02
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GPIOF->DATA_Bits[LED_BLUE] = 0xFFU; // turn the Blue LED on
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GPIOF->DATA_Bits[LED_BLUE] = 0U; // turn the Blue LED off
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#ifdef Q_SPY
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QF_INT_ENABLE();
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QS::rxParse(); // parse all the received bytes
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if ((UART0->FR & UART_FR_TXFE) != 0U) { // TX done?
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uint16_t fifo = UART_TXFIFO_DEPTH; // max bytes we can accept
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uint8_t const *block;
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QF_INT_DISABLE();
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block = QS::getBlock(&fifo); // try to get next block to transmit
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QF_INT_ENABLE();
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while (fifo-- != 0U) { // any bytes in the block?
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UART0->DR = *block++; // put into the FIFO
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}
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}
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#elif defined NDEBUG
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// Put the CPU and peripherals to the low-power mode.
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// you might need to customize the clock management for your application,
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// see the datasheet for your particular Cortex-M MCU.
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//
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QV_CPU_SLEEP(); // atomically go to sleep and enable interrupts
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#else
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QF_INT_ENABLE(); // just enable interrupts
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#endif
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}
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//............................................................................
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extern "C" void Q_onAssert(char const *module, int loc) {
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//
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// NOTE: add here your application-specific error handling
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//
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(void)module;
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(void)loc;
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QS_ASSERTION(module, loc, static_cast<uint32_t>(10000U));
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NVIC_SystemReset();
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}
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// QS callbacks ==============================================================
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#ifdef Q_SPY
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//............................................................................
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bool QS::onStartup(void const *arg) {
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static uint8_t qsBuf[2*1024]; // buffer for Quantum Spy
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static uint8_t qsRxBuf[100]; // buffer for QS receive channel
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uint32_t tmp;
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initBuf(qsBuf, sizeof(qsBuf));
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rxInitBuf(qsRxBuf, sizeof(qsRxBuf));
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// enable clock for UART0 and GPIOA (used by UART0 pins)
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SYSCTL->RCGCUART |= (1U << 0); // enable Run mode for UART0
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SYSCTL->RCGCGPIO |= (1U << 0); // enable Run mode for GPIOA
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// configure UART0 pins for UART operation
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tmp = (1U << 0) | (1U << 1);
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GPIOA->DIR &= ~tmp;
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GPIOA->SLR &= ~tmp;
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GPIOA->ODR &= ~tmp;
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GPIOA->PUR &= ~tmp;
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GPIOA->PDR &= ~tmp;
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GPIOA->AMSEL &= ~tmp; // disable analog function on the pins
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GPIOA->AFSEL |= tmp; // enable ALT function on the pins
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GPIOA->DEN |= tmp; // enable digital I/O on the pins
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GPIOA->PCTL &= ~0x00U;
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GPIOA->PCTL |= 0x11U;
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// configure the UART for the desired baud rate, 8-N-1 operation
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tmp = (((SystemCoreClock * 8U) / UART_BAUD_RATE) + 1U) / 2U;
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UART0->IBRD = tmp / 64U;
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UART0->FBRD = tmp % 64U;
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UART0->LCRH = (0x3U << 5); // configure 8-N-1 operation
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UART0->LCRH |= (0x1U << 4); // enable FIFOs
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UART0->CTL = (1U << 0) // UART enable
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| (1U << 8) // UART TX enable
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| (1U << 9); // UART RX enable
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// configure UART interrupts (for the RX channel)
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UART0->IM |= (1U << 4) | (1U << 6); // enable RX and RX-TO interrupt
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UART0->IFLS |= (0x2U << 2); // interrupt on RX FIFO half-full
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// NOTE: do not enable the UART0 interrupt yet. Wait till QF_onStartup()
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DPP::QS_tickPeriod_ = SystemCoreClock / DPP::BSP::TICKS_PER_SEC;
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DPP::QS_tickTime_ = DPP::QS_tickPeriod_; // to start the timestamp at zero
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// setup the QS filters...
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QS_FILTER_ON(QS_QEP_STATE_ENTRY);
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QS_FILTER_ON(QS_QEP_STATE_EXIT);
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QS_FILTER_ON(QS_QEP_STATE_INIT);
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QS_FILTER_ON(QS_QEP_INIT_TRAN);
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QS_FILTER_ON(QS_QEP_INTERN_TRAN);
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QS_FILTER_ON(QS_QEP_TRAN);
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QS_FILTER_ON(QS_QEP_IGNORED);
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QS_FILTER_ON(QS_QEP_DISPATCH);
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QS_FILTER_ON(QS_QEP_UNHANDLED);
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QS_FILTER_ON(DPP::PHILO_STAT);
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QS_FILTER_ON(DPP::COMMAND_STAT);
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return true; // return success
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}
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//............................................................................
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void QS::onCleanup(void) {
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}
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//............................................................................
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QSTimeCtr QS::onGetTime(void) { // NOTE: invoked with interrupts DISABLED
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if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0) { // not set?
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return DPP::QS_tickTime_ - static_cast<QSTimeCtr>(SysTick->VAL);
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}
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else { // the rollover occured, but the SysTick_ISR did not run yet
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return DPP::QS_tickTime_ + DPP::QS_tickPeriod_
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- static_cast<QSTimeCtr>(SysTick->VAL);
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}
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}
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//............................................................................
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void QS::onFlush(void) {
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uint16_t fifo = UART_TXFIFO_DEPTH; // Tx FIFO depth
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uint8_t const *block;
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QF_INT_DISABLE();
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while ((block = getBlock(&fifo)) != static_cast<uint8_t *>(0)) {
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QF_INT_ENABLE();
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// busy-wait until TX FIFO empty
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while ((UART0->FR & UART_FR_TXFE) == 0U) {
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}
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while (fifo-- != 0U) { // any bytes in the block?
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UART0->DR = *block++; // put into the TX FIFO
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}
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fifo = UART_TXFIFO_DEPTH; // re-load the Tx FIFO depth
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QF_INT_DISABLE();
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}
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QF_INT_ENABLE();
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}
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//............................................................................
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//! callback function to reset the target (to be implemented in the BSP)
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void QS::onReset(void) {
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NVIC_SystemReset();
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}
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//............................................................................
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//! callback function to execute a user command (to be implemented in BSP)
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extern "C" void assert_failed(char const *module, int loc);
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void QS::onCommand(uint8_t cmdId, uint32_t param) {
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(void)cmdId;
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(void)param;
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// application-specific record
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QS_BEGIN(DPP::COMMAND_STAT, static_cast<void *>(0))
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QS_U8(2, cmdId);
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QS_U32(8, param);
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QS_END()
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if (cmdId == 10U) {
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assert_failed("QS_onCommand", 11);
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}
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}
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#endif // Q_SPY
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//----------------------------------------------------------------------------
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} // namespace QP
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//****************************************************************************
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// NOTE00:
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// The QF_AWARE_ISR_CMSIS_PRI constant from the QF port specifies the highest
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// ISR priority that is disabled by the QF framework. The value is suitable
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// for the NVIC_SetPriority() CMSIS function.
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//
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// Only ISRs prioritized at or below the QF_AWARE_ISR_CMSIS_PRI level (i.e.,
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// with the numerical values of priorities equal or higher than
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// QF_AWARE_ISR_CMSIS_PRI) are allowed to call the QK_ISR_ENTRY/QK_ISR_ENTRY
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// macros or any other QF/QK services. These ISRs are "QF-aware".
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//
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// Conversely, any ISRs prioritized above the QF_AWARE_ISR_CMSIS_PRI priority
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// level (i.e., with the numerical values of priorities less than
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// QF_AWARE_ISR_CMSIS_PRI) are never disabled and are not aware of the kernel.
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// Such "QF-unaware" ISRs cannot call any QF/QK services. In particular they
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// can NOT call the macros QK_ISR_ENTRY/QK_ISR_ENTRY. The only mechanism
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// by which a "QF-unaware" ISR can communicate with the QF framework is by
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// triggering a "QF-aware" ISR, which can post/publish events.
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//
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// NOTE01:
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// The QV:onIdle() callback is called with interrupts disabled, because the
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// determination of the idle condition might change by any interrupt posting
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// an event. QV::onIdle() must internally enable interrupts, ideally
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// atomically with putting the CPU to the power-saving mode.
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//
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// NOTE02:
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// The User LED is used to visualize the idle loop activity. The brightness
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// of the LED is proportional to the frequency of invcations of the idle loop.
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// Please note that the LED is toggled with interrupts locked, so no interrupt
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// execution time contributes to the brightness of the User LED.
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//
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