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381 lines
16 KiB
C++
381 lines
16 KiB
C++
//////////////////////////////////////////////////////////////////////////////
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// Product: BSP for MCF52223-SK board, with the Vanilla kernel
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// Last Updated for Version: 4.0.00
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// Date of the Last Update: Jun 08, 2008
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//
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// Q u a n t u m L e a P s
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// ---------------------------
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// innovating embedded systems
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//
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// Copyright (C) 2002-2008 Quantum Leaps, LLC. All rights reserved.
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//
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// This software may be distributed and modified under the terms of the GNU
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// General Public License version 2 (GPL) as published by the Free Software
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// Foundation and appearing in the file GPL.TXT included in the packaging of
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// this file. Please note that GPL Section 2[b] requires that all works based
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// on this software must also be made publicly available under the terms of
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// the GPL ("Copyleft").
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//
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// Alternatively, this software may be distributed and modified under the
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// terms of Quantum Leaps commercial licenses, which expressly supersede
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// the GPL and are specifically designed for licensees interested in
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// retaining the proprietary status of their code.
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//
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// Contact information:
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// Quantum Leaps Web site: http://www.quantum-leaps.com
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// e-mail: info@quantum-leaps.com
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//////////////////////////////////////////////////////////////////////////////
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#include "qp_port.h"
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#include "dpp.h"
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#include "bsp.h"
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#include <io52223.h> // MCF52223 MCU
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#include "intr_handlers.h"
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//#include "icm_drv_stat.h"
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Q_DEFINE_THIS_FILE
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// Local-scope objects -------------------------------------------------------
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static uint32_t l_delay = 0UL; // limit for the loop counter in busyDelay()
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#define SYS_CLK 48000000L
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#define PER_CLK (SYS_CLK/2)
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#define AN_TR_PIN MCF_GPIO_PORTAN_PORTAN0
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#define AN_TR_CHANNEL 0
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// interrupt IDs ...
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#define INTR_ID_EPF1 ( 1+64)
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#define INTR_ID_EPF2 ( 2+64)
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#define INTR_ID_EPF3 ( 3+64)
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#define INTR_ID_EPF4 ( 4+64)
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#define INTR_ID_EPF5 ( 5+64)
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#define INTR_ID_EPF6 ( 6+64)
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#define INTR_ID_EPF7 ( 7+64)
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#define INTR_ID_SWT ( 8+64)
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#define INTR_ID_DMA0 ( 9+64)
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#define INTR_ID_DMA1 (10+64)
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#define INTR_ID_DMA2 (11+64)
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#define INTR_ID_DMA3 (12+64)
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#define INTR_ID_UART0 (13+64)
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#define INTR_ID_UART1 (14+64)
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#define INTR_ID_UART2 (15+64)
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#define INTR_ID_I2S (17+64)
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#define INTR_ID_QSPI (18+64)
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#define INTR_ID_DTIM0 (19+64)
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#define INTR_ID_DTIM1 (20+64)
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#define INTR_ID_DTIM2 (21+64)
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#define INTR_ID_DTIM3 (22+64)
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#define INTR_ID_GPT_OVF (41+64)
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#define INTR_ID_GPT_PAI (42+64)
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#define INTR_ID_GPT_PAOVF (43+64)
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#define INTR_ID_GPT_C0 (44+64)
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#define INTR_ID_GPT_C1 (45+64)
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#define INTR_ID_GPT_C2 (46+64)
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#define INTR_ID_GPT_C3 (47+64)
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#define INTR_ID_GPT_LVD (48+64)
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#define INTR_ID_ADC_A (49+64)
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#define INTR_ID_ADC_B (50+64)
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#define INTR_ID_ADC (51+64)
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#define INTR_ID_PWM (52+64)
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#define INTR_ID_USB (53+64)
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#define INTR_ID_PIT0 (55+64)
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#define INTR_ID_PIT1 (56+64)
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#define INTR_ID_CFM_BE (59+64)
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#define INTR_ID_CFM_CC (60+64)
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#define INTR_ID_CFM_PV (61+64)
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#define INTR_ID_CFM_AE (62+64)
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#define INTR_ID_RTC (63+64)
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#define PIT_PERIOD (PER_CLK / (BSP_TICKS_PER_SEC * 16))
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#define PIT0_LEVEL 2
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#ifdef Q_SPY
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QSTimeCtr QS_tickTime;
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#define UART_BAUD 115200
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enum AppRecords { // application-specific trace records
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PHILO_STAT = QS_USER
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};
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#endif
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//............................................................................
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extern "C" __interrupt void PIT0_IntrHandler(void) {
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MCF_PIT0_PCSR |= MCF_PIT_PCSR_PIF; // clear the interrupt source
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#ifdef Q_SPY
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QS_tickTime += PIT_PERIOD; // add the rollover
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#endif
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QF::tick(); // process all armed time events
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}
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//............................................................................
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void BSP_init(int argc, char *argv[]) {
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(void)argc; // unused: avoid the complier warning
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(void)argv; // unused: avoid the compiler warning
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// initialize the Interrupt Control Module
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MCF_SCM_PPMRC = MCF_SCM_PPMRC_ENABLE_INTC; // enable ICM clock
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MCF_INTC0_IMRH = MCF_INTC0_IMRL = 0xFFFFFFFF; // mask all interrupts
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MCF_INTC0_INTFRCH = MCF_INTC0_INTFRCL = 0; // clear forced interrupts
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// initialize the LEDs lines...
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MCF_GPIO_PANPAR &= ~0xFE;
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MCF_GPIO_SETAN = 0xFE;
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MCF_GPIO_DDRAN |= 0xFE;
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MCF_GPIO_PDDPAR &= ~0xFF;
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MCF_GPIO_SETDD = 0xFF;
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MCF_GPIO_DDRDD |= 0xFF;
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MCF_GPIO_PTAPAR &= ~0x02;
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MCF_GPIO_SETTA = 0x02;
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MCF_GPIO_DDRTA |= 0x02;
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// configure the low-power mode
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MCF_PMM_LPCR = MCF_PMM_LPCR_LPMD_DOZE;
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MCF_PMM_LPICR = MCF_PMM_LPICR_XLPM_IPL(0); // any interrupt wakes up
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if (QS_INIT((void *)0) == 0) { // initialize the QS software tracing
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Q_ERROR();
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}
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}
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//............................................................................
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void BSP_displyPhilStat(uint8_t n, char const *stat) {
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if (stat[0] == 'e') {
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MCF_GPIO_CLRAN = ~(2UL << n);
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}
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else {
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MCF_GPIO_SETAN = (2UL << n);
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}
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QS_BEGIN(PHILO_STAT, AO_Philo[n]) // application-specific record begin
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QS_U8(1, n); // Philosopher number
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QS_STR(stat); // Philosopher status
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QS_END()
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}
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//............................................................................
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void BSP_busyDelay(void) {
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uint32_t volatile i = l_delay;
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while (i-- > 0UL) { // busy-wait loop
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}
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}
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//............................................................................
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void QF::onStartup(void) {
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MCF_SCM_PPMRC = MCF_SCM_PPMRC_ENABLE_PIT0; // enable PIT0 clock
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// configure PIT0 Ctrl and status register
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MCF_PIT0_PCSR = MCF_PIT_PCSR_PRE(4) // prescaler 1/16
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| MCF_PIT_PCSR_RLD // enable reload
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| MCF_PIT_PCSR_PIF // clear pending interrupt
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| MCF_PIT_PCSR_PIE // enable interrupt
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| MCF_PIT_PCSR_OVW // enable overwrite
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| MCF_PIT_PCSR_DBG; // enable debug mode
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MCF_PIT0_PMR = PIT_PERIOD - 1; // set the PMR for the desired rate
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// configure PIT0 interrupt
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*(&MCF_INTC0_ICR01 + INTR_ID_PIT0 - 64 - 1) = (PIT0_LEVEL << 3);
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// enable PIT0 interrupt
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MCF_INTC0_IMRH &= ~(1UL << (INTR_ID_PIT0 & 0x1F));
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MCF_PIT0_PCSR |= MCF_PIT_PCSR_EN; // enable PIC0 counting
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__enable_interrupts(); // Global interrupts enable
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}
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//............................................................................
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void QF::onCleanup(void) {
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}
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//............................................................................
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void QF::onIdle(QF_INT_KEY_TYPE key) { // interrupts LOCKED, NOTE01
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// toggle the LED-16 on and then off, see NOTE02
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MCF_GPIO_CLRTA = ~0x02;
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MCF_GPIO_SETTA = 0x02;
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#ifdef Q_SPY
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QF_INT_UNLOCK(key);
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if ((MCF_DMA3_BCR & 0x00FFFFFF) == 0) { // DMA byte counter zero?
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uint16_t len = 0xFFFF; // request as many bytes as possible
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uint8_t const *block;
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QF_INT_LOCK(key);
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block = QS::getBlock(&len); // try to get next block to transmit
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QF_INT_UNLOCK(key);
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if (block != (uint8_t *)0) {
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MCF_DMA3_DCR = 0x00; // clear the DCR to avoid CE error
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MCF_DMA3_DSR = 0x01; // reset the DSR
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MCF_DMA3_SAR = (uint32_t)block; // set the source
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MCF_DMA3_DAR = (uint32_t)&MCF_UART_UTB(2); // destination UART2
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MCF_DMA3_BCR = MCF_DMA_BCR_BCR(len); // byte counter
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// external Request, cycle Steal, dest & source = 8 bit
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// dest address NOT incremented source incremented by 1
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MCF_DMA3_DCR = MCF_DMA_DCR_EEXT
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| MCF_DMA_DCR_CS
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| MCF_DMA_DCR_SINC
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| MCF_DMA_DCR_SSIZE(01)
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| MCF_DMA_DCR_DSIZE(01);
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}
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}
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else {
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QF_INT_UNLOCK(key); // unlock interrupts
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}
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#elif defined NDEBUG
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// Put the CPU and peripherals to the low-power mode.
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// you might need to customize the clock management for your application,
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// see the ColdFire Reference Manual for your particular device.
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__stop(0x2000); // privileged STOP instruction
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#else
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QF_INT_UNLOCK(key); // unlock the interrupts
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#endif
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}
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//............................................................................
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void Q_onAssert(char const Q_ROM * const Q_ROM_VAR file, int line) {
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(void)file; // avoid compiler warning
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(void)line; // avoid compiler warning
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__disable_interrupts(); // make sure that all interrupts are disabled
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for (;;) { // NOTE: replace the loop with reset for final version
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}
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}
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//----------------------------------------------------------------------------
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#ifdef Q_SPY
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//............................................................................
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uint8_t QS::onStartup(void const *arg) {
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static uint8_t qsBuf[2*1024]; // buffer for Quantum Spy
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extern uint32_t __RAMBEGIN;
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initBuf(qsBuf, sizeof(qsBuf));
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// set port UC to initialize UTXD2
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MCF_GPIO_PUCPAR = MCF_GPIO_PUCPAR_UTXD2_UTXD2; // config UTXD2 pin
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MCF_UART2_UCR = MCF_UART_UCR_RESET_TX; // reset Transmitter
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MCF_UART2_UCR = MCF_UART_UCR_RESET_MR; // reset the Mode Register
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// config no parity, 8-bits, no echo, no loopback, 1 stop bit
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MCF_UART2_UMR1 = MCF_UART_UMR_PM_NONE | MCF_UART_UMR_BC_8
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| MCF_UART_UMR_CM_NORMAL | MCF_UART_UMR_SB_STOP_BITS_1;
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// set the Tx baud rate generator from the SYSTEM CLOCK
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MCF_UART2_UCSR = MCF_UART_UCSR_TCS_SYS_CLK;
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MCF_UART2_UBG1 = (uint8_t)((SYS_CLK / (UART_BAUD * 32)) >> 8);
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MCF_UART2_UBG2 = (uint8_t)(SYS_CLK / (UART_BAUD * 32));
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MCF_UART2_UCR = MCF_UART_UCR_TX_ENABLED; // enable transmitter
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// set BDE for DMA access in MCF_SCM_RAMBAR
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MCF_SCM_RAMBAR = (uint32_t)&__RAMBEGIN | (MCF_SCM_RAMBAR_BDE | 0x1);
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MCF_SCM_MPR |= 0x04; // Master Privilege Register bit-2 DMA master
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MCF_SCM_DMAREQC|= MCF_SCM_DMAREQC_DMAC3(0x0E); // DMA3 for UART2 TX
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MCF_DMA3_DCR = 0x00; // clear the DCR to avoid CE error
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MCF_DMA3_DSR = 0x01; // reset the DSR
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QS_tickTime = PIT_PERIOD - 1; // to start the timestamp at zero
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// setup the QS filters...
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QS_FILTER_ON(QS_ALL_RECORDS);
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// QS_FILTER_OFF(QS_QEP_STATE_EMPTY);
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// QS_FILTER_OFF(QS_QEP_STATE_ENTRY);
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// QS_FILTER_OFF(QS_QEP_STATE_EXIT);
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// QS_FILTER_OFF(QS_QEP_STATE_INIT);
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// QS_FILTER_OFF(QS_QEP_INIT_TRAN);
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// QS_FILTER_OFF(QS_QEP_INTERN_TRAN);
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// QS_FILTER_OFF(QS_QEP_TRAN);
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// QS_FILTER_OFF(QS_QEP_dummyD);
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QS_FILTER_OFF(QS_QF_ACTIVE_ADD);
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QS_FILTER_OFF(QS_QF_ACTIVE_REMOVE);
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QS_FILTER_OFF(QS_QF_ACTIVE_SUBSCRIBE);
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QS_FILTER_OFF(QS_QF_ACTIVE_UNSUBSCRIBE);
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QS_FILTER_OFF(QS_QF_ACTIVE_POST_FIFO);
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QS_FILTER_OFF(QS_QF_ACTIVE_POST_LIFO);
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QS_FILTER_OFF(QS_QF_ACTIVE_GET);
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QS_FILTER_OFF(QS_QF_ACTIVE_GET_LAST);
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QS_FILTER_OFF(QS_QF_EQUEUE_INIT);
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QS_FILTER_OFF(QS_QF_EQUEUE_POST_FIFO);
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QS_FILTER_OFF(QS_QF_EQUEUE_POST_LIFO);
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QS_FILTER_OFF(QS_QF_EQUEUE_GET);
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QS_FILTER_OFF(QS_QF_EQUEUE_GET_LAST);
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QS_FILTER_OFF(QS_QF_MPOOL_INIT);
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QS_FILTER_OFF(QS_QF_MPOOL_GET);
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QS_FILTER_OFF(QS_QF_MPOOL_PUT);
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QS_FILTER_OFF(QS_QF_PUBLISH);
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QS_FILTER_OFF(QS_QF_NEW);
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QS_FILTER_OFF(QS_QF_GC_ATTEMPT);
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QS_FILTER_OFF(QS_QF_GC);
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// QS_FILTER_OFF(QS_QF_TICK);
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QS_FILTER_OFF(QS_QF_TIMEEVT_ARM);
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QS_FILTER_OFF(QS_QF_TIMEEVT_AUTO_DISARM);
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QS_FILTER_OFF(QS_QF_TIMEEVT_DISARM_ATTEMPT);
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QS_FILTER_OFF(QS_QF_TIMEEVT_DISARM);
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QS_FILTER_OFF(QS_QF_TIMEEVT_REARM);
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QS_FILTER_OFF(QS_QF_TIMEEVT_POST);
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QS_FILTER_OFF(QS_QF_INT_LOCK);
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QS_FILTER_OFF(QS_QF_INT_UNLOCK);
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QS_FILTER_OFF(QS_QF_ISR_ENTRY);
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QS_FILTER_OFF(QS_QF_ISR_EXIT);
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return (uint8_t)1; // return success
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}
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//............................................................................
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void QS::onCleanup(void) {
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}
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//............................................................................
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QSTimeCtr QS::onGetTime(void) { // invoked with interrupts locked
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if ((MCF_PIT0_PCSR & MCF_PIT_PCSR_PIF) == 0) { // no rollover?
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return QS_tickTime - (QSTimeCtr)MCF_PIT0_PCNTR;
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}
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else { // the rollover occured, but PIT0_IntrHandler() did not run yet
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return QS_tickTime + PIT_PERIOD
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- (QSTimeCtr)(QSTimeCtr)MCF_PIT0_PCNTR;
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}
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}
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//............................................................................
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void QS::onFlush(void) {
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uint16_t len = 0xFFFF; // request as much as possible
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uint8_t const *block;
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QF_INT_KEY_TYPE intKeyLock;
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QF_INT_LOCK(intKeyLock);
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while ((block = getBlock(&len)) != (uint8_t *)0) {
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QF_INT_UNLOCK(intKeyLock);
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// wait in-line while DMA byte counter not zero
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while ((MCF_DMA3_BCR & 0x00FFFFFF) != 0) {
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}
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MCF_DMA3_DCR = 0x00; // clear the DCR to avoid CE error
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MCF_DMA3_DSR = 0x01; // reset the DSR
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MCF_DMA3_SAR = (uint32_t)block; // set the source
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MCF_DMA3_DAR = (uint32_t)&MCF_UART_UTB(2); // destination UART2
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MCF_DMA3_BCR = MCF_DMA_BCR_BCR(len); // byte counter
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// external Request, cycle Steal, dest & source = 8 bit
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// dest address NOT incremented source incremented by 1
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MCF_DMA3_DCR = MCF_DMA_DCR_EEXT
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| MCF_DMA_DCR_CS
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| MCF_DMA_DCR_SINC
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| MCF_DMA_DCR_SSIZE(01)
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| MCF_DMA_DCR_DSIZE(01);
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len = 0xFFFF; // re-load the length
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QF_INT_LOCK(intKeyLock);
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}
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QF_INT_UNLOCK(intKeyLock);
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}
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#endif // Q_SPY
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//----------------------------------------------------------------------------
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//////////////////////////////////////////////////////////////////////////////
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// NOTE01:
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// The QF::onIdle() callback is called with interrupts locked, because the
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// determination of the idle condition might change by any interrupt posting
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// an event. QF::onIdle() must internally unlock interrupts, ideally
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// atomically with putting the CPU to the power-saving mode.
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//
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// NOTE02:
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// The User LED is used to visualize the idle loop activity. The brightness
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// of the LED is proportional to the frequency of invcations of the idle loop.
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// Please note that the LED is toggled with interrupts locked, so no interrupt
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// execution time contributes to the brightness of the User LED.
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//
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