mirror of
https://github.com/QuantumLeaps/qpcpp.git
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148 lines
7.0 KiB
C
148 lines
7.0 KiB
C
/* ============================================================================
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* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2008
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*
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* Use of this software is controlled by the terms and conditions found in the
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* license agreement under which this software has been supplied.
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* ============================================================================
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*/
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/** @file soc.h
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*
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* @brief This file contains the Chip Description for VC5505
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*
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* Path: \(CSLPATH)\inc
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*/
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/* ============================================================================
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* Revision History
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* ================
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* 11-Aug-2008 Created
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* 29 -Sept -2008 Added cslr_gpio.h header file ,
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* GPIO Overlay structure and Base Address
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* 15 -Oct -2008 Added cslr_cpu.h header file ,
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* CPU Overlay structure and Base Address
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* ============================================================================
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*/
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#ifndef _SOC_H
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#define _SOC_H
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#include <cslr.h>
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#include <tistdtypes.h>
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#include <cslr_sysctrl.h>
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#include <cslr_cpu.h>
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/*****************************************************************************\
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* Include files for all the modules in the device
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\*****************************************************************************/
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#include "cslr_i2c.h"
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#include "cslr_i2s.h"
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#include "cslr_emif.h"
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#include "cslr_uart.h"
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#include "cslr_spi.h"
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#include "cslr_mmcsd.h"
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#include "cslr_lcdc.h"
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#include "cslr_rtc.h"
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#include "cslr_dma.h"
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#include "cslr_sar.h"
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#include "cslr_usb.h"
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#include "cslr_gpio.h"
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#include "cslr_tim.h"
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#include "cslr_wdt.h"
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#include "csl_general.h"
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/*****************************************************************************\
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* Peripheral Instance counts
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\*****************************************************************************/
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#define CSL_DMA_PER_CNT 4
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#define CSL_EMIF_PER_CNT 1
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#define CSL_I2C_PER_CNT 1
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#define CSL_I2S_PER_CNT 4
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#define CSL_LCDC_PER_CNT 1
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#define CSL_MMCSD_PER_CNT 2
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#define CSL_PLL_PER_CNT 1
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#define CSL_RTC_PER_CNT 1
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#define CSL_SAR_PER_CNT 1
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#define CSL_SPI_PER_CNT 1
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#define CSL_UART_PER_CNT 1
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#define CSL_USB_PER_CNT 1
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#define CSL_TIM_PER_CNT 3
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#define CSL_WDT_PER_CNT 1
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/*****************************************************************************\
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* Peripheral Overlay Structures
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\*****************************************************************************/
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typedef volatile ioport CSL_UsbRegs * CSL_UsbRegsOvly;
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typedef volatile ioport CSL_I2cRegs * CSL_I2cRegsOvly;
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typedef volatile ioport CSL_I2sRegs * CSL_I2sRegsOvly;
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typedef volatile ioport CSL_EmifRegs * CSL_EmifRegsOvly;
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typedef volatile ioport CSL_UartRegs * CSL_UartRegsOvly;
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typedef volatile ioport CSL_SpiRegs * CSL_SpiRegsOvly;
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typedef volatile ioport CSL_MmcsdRegs * CSL_MmcsdRegsOvly;
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typedef volatile ioport CSL_LcdcRegs * CSL_LcdcRegsOvly;
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typedef volatile ioport CSL_RtcRegs * CSL_RtcRegsOvly;
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typedef volatile ioport CSL_AnactrlRegs * CSL_SarRegsOvly;
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typedef volatile ioport CSL_GpioRegs * CSL_GpioRegsOvly;
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typedef volatile ioport CSL_SysRegs * CSL_SysRegsOvly;
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typedef volatile ioport CSL_DmaRegs * CSL_DmaRegsOvly;
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typedef volatile CSL_CpuRegs * CSL_CpuRegsOvly;
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typedef volatile ioport CSL_TimRegs * CSL_TimRegsOvly;
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typedef volatile ioport CSL_WdtRegs * CSL_WdtRegsOvly;
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/*****************************************************************************\
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* Peripheral Base Address
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\*****************************************************************************/
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#define CSL_USB_REGS ((CSL_UsbRegsOvly) 0x8000)
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#define CSL_SAR_REGS ((CSL_SarRegsOvly) 0x7000)
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#define CSL_EMIF_REGS ((CSL_EmifRegsOvly) 0x1000)
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#define CSL_I2C_0_REGS ((CSL_I2cRegsOvly) 0x1A00)
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#define CSL_I2S0_REGS ((CSL_I2sRegsOvly) 0x2800)
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#define CSL_I2S1_REGS ((CSL_I2sRegsOvly) 0x2900)
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#define CSL_I2S2_REGS ((CSL_I2sRegsOvly) 0x2A00)
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#define CSL_I2S3_REGS ((CSL_I2sRegsOvly) 0x2B00)
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#define CSL_UART_REGS ((CSL_UartRegsOvly) 0x1B00)
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#define CSL_SPI_REGS ((CSL_SpiRegsOvly) 0x3000)
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#define CSL_MMCSD0_REGS ((CSL_MmcsdRegsOvly)0x3A00)
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#define CSL_MMCSD1_REGS ((CSL_MmcsdRegsOvly)0x3B00)
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#define CSL_LCDC_REGS ((CSL_LcdcRegsOvly) 0x2E00)
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#define CSL_RTC_REGS ((CSL_RtcRegsOvly) 0x1900)
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#define CSL_DMA0_REGS ((CSL_DmaRegsOvly) 0x0C00)
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#define CSL_DMA1_REGS ((CSL_DmaRegsOvly) 0x0D00)
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#define CSL_DMA2_REGS ((CSL_DmaRegsOvly) 0x0E00)
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#define CSL_DMA3_REGS ((CSL_DmaRegsOvly) 0x0F00)
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#define CSL_GPIO_REGS ((CSL_GpioRegsOvly) 0x1c00)
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#define CSL_SYSCTRL_REGS ((CSL_SysRegsOvly) 0x1c00)
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#define CSL_CPU_REGS ((CSL_CpuRegsOvly) 0x0000)
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#define CSL_WDT_REGS ((CSL_WdtRegsOvly) 0x1880)
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#define CSL_TIM_0_REGS ((CSL_TimRegsOvly) 0x1810)
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#define CSL_TIM_1_REGS ((CSL_TimRegsOvly) 0x1850)
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#define CSL_TIM_2_REGS ((CSL_TimRegsOvly) 0x1890)
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/** \brief EMIF CS2 Base address */
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#define CSL_EMIF_CS2_DATA_BASE_ADDR (0x400000u)
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/** \brief EMIF CS3 Base address */
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#define CSL_EMIF_CS3_DATA_BASE_ADDR (0x600000u)
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/** \brief EMIF CS4 Base address */
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#define CSL_EMIF_CS4_DATA_BASE_ADDR (0x700000u)
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/** \brief EMIF CS5 Base address */
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#define CSL_EMIF_CS5_DATA_BASE_ADDR (0x780000u)
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/** \brief EMIF CSx address offset - Default A11 used to drive ALE */
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#define CSL_EMIF_CSx_ADDR_OFFSET (0x1000u)
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/** \brief EMIF CS2 command offset - Default A12 used to drive CLE */
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#define CSL_EMIF_CSx_CMD_OFFSET (0x2000u)
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/** \brief NAND CE0 address for DMA access - EMIF CS2 */
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#define CSL_NAND_CE0_ADDR (0x2000000u)
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/** \brief NAND CE1 address for DMA access - EMIF CS3 */
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#define CSL_NAND_CE1_ADDR (0x3000000u)
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/** \brief ASYNC CE0 address for DMA access - EMIF CS4 */
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#define CSL_ASYNC_CE0_ADDR (0x4000000u)
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/** \brief ASYNC CE1 address for DMA access - EMIF CS5 */
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#define CSL_ASYNC_CE1_ADDR (0x5000000u)
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/** \brief Timer intreupt aggregation flag register */
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#define CSL_IAFR_REGS (0x1C14)
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#endif // _SOC_H
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